Project Power

T.HARIKA Contact No. : - 078********

E-mail:- *************@*****.*** M. Tech, VLSI Design

VIT UNIVERSITY,VELLORE

TAMIL NADU

CAREER OBJECTIVE

Reliable and resourceful VLSI engineer and to be an adept multitasker who thrives in a high pressure work environment and toserve the nation and company with my skills and knowledge

OBJECTIVEOF RESUME

Being a final year post graduation student in VLSI stream, I am seeking for an internship in your company, that requires applying my analytical skills in the field of VLSI

SUMMARY

Strong communication, collaboration & interpersonal skills with proficiency in grasping new technical concepts quickly and utilizing them in an effective manner capability to implement new ideas.

Ability in handling multiple priorities, with a bias for action and a genuine interest in personal and professional development.

ACADEMIC CREDENTIALS

S.No

Course Studied

School/College

Board/University

Year of study

Aggregate%

1

2

3

4

5

6

1

M.Tech VLSI DESIGN

Vit University Vellore Tamilnadu

Vit University Vellore Tamilnadu

2014-2016

CGPA OF 7

1

B.Tech

Intell engineering college

JNTUniversity, Anantapur

2010-2014

71

2

Intermediate

NarayanaJunior College

Board of Intermediate

2008-2010

94

3

SSC

St JosephHigh School

Boardof Secondary Education

2008

88

Distinguished Merits :- Awarded National Merit Scholar Ship in the year 2010 for acquiring 94% Marks in Intermediate and Awarded Best Student award with Merit scholarship.

Excellent track record and no adverse remarks

PROJECT DETAILS

M.TECH PROJECTS:

1)NAME OF PROJECT:-DESIGNING OF LOW POWER HIGH SPEED MAC WITH BYPASSING MULTIPLIER AND ERROR TOLERANT ADDER

ABOUT PROJECT:-

This project helps to implement a MAC unit, MAC unit, as we know, finds its use in all most all the electronic circuits. So there is a need to reduce power consumed by mac unit. we are going to adopt an already existing low power technique known as equal operand bypassing in the multiplier part and error tolerant in the adder part. This bypassing technique mainly aims at reducing power consumption by passing the operands directly rather than summing them up. This reduces power consumption considerably. In the adder part we are trying to suppress the carry propagation and hence reducing the power and delay. This MAC is unique in the way that both the multiplier and adder have reduced power consumption. Since the output of the adder generates little amount of error, this MAC finds its use in applications where in little amount of error can be tolerated. One such application is in the digital processing systems where in the digital data processed from the analog signals contain bit of error and when converted back to analog domain contain the same errors but are not perceived at the receiver’s end. The project has been implemented through cadence NClaunch and library used is TSMC 90nm

AIM OF PROJECT:-To have a great deal of reduction in power and also there is an acceptable accuracy with only a little amount of error

NAME OF PROJECT:-DESIGNING OF LOW POWER MAC BY USING BYPASSING MULTIPLIER

ABOUT PROJECT:-

This project helps to implement a MAC unit which mainly aims at reducing area and power. In this project the MAC unit is implemented by building a parallel multiplier with bypassing technique. In the multiplier block we are bypassing the operands if they are equal i.e implementing it in the form of an EXOR gate.As a result power dissipation and circuitry can be reduced. Also the adder circuit in MAC is built using carry save adders which aim at giving outputs with less delay. We are implementing this improved circuitry in QUARTUS II which is used for power calculation and MODELSIM which is used for simulation. This resulted in improvement in power dissipation

ACHEIVEMENTS OF PROJECT: This Project has been awarded an exceptional grade in vit university and selected for oral presentation in university

AIM OF PROJECT:-To have a great reduction in power and area

B.TECH PROJECT:

NAME OF PROJECT:-IMPLEMENTATION OF HIGH SPEED FIR FILTER IN DSP APPLICATIONS

ABOUT PROJECT:-

This project describes an approach to the implementation of digital filter based on VLSI which is flexible and provides performance comparable or superior to traditional approaches, area efficient, high speed, reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response Finite Impulse Response(FIR) filters.

ROLE IN PROJECT:-TEAM LEADER

AIM OF PROJECT:-

To obtain high speed fir filter for signal processing

SIMULATION OF SOFTWARES

EDA TOOLS KNOWN:

1) MENTOR GRAPHICS MODELSIM

2) ALTERA QUARTRUS II

3)Cadence virtuoso,NClaunch,SoC encounter,

MATLAB(R2013B)

PROGRAMMING LANGUAGES

SOFTWARE PROGRAMMING LANGUAGES: C

ASSEMBLY LANGUAGE PROGRAMMING : 8051

HARDWARE DESCRIPTION LANGUAGES : VERILOG,VHDL

SCRIPTING LANGUAGES: PERL,TCL

OPERATING SYSTEMS KNOWN

WINDOWS

LINUX

EXTRA- CURRICULAR & ACHIEVEMENTS

Have proficiency in English, Telugu.

Certified by Value Point Academy, Bangalore in Soft Skills

Completed Course on Effective Communication Skills

Was a member of helpageindia

Got merit scholar ship in science talent test held in st.joseph public school

Served as school peoples representative in st.joseph public school

And class representative for intel engineering college

Presented a seminar on digital water marking in intel engineering college

FIELD OF INTEREST

Front end design

Back end design

PERSONAL DOSSIER

NAME : T.HARIKA

FATHER’S NAME : T.RAJENDRA PRASAD.

GENDER : FEMALE

MARITAL STATUS : SINGLE

DATE OF BIRTH : 31st DECEMBER-1993

RELIGION : INDIAN HINDU

STRENGTHS:-

good communication and interpersonal skills

honesty

social in nature

excessive zeal to learn new things

adaptive to many situations

good knowledge in VLSI design flow

HOBBIES:-

philately

dancing

DECLARATION

I do hereby declare that the above information is true to the best of my knowledge.

Place: vellore T.HARIKA

Date: 17-5-2015

Contact this candidate