VLSI Design and Embedded Systems
Resume:
RESUME
Name : Priyanka T N
Email : *******************@*****.***
Mobile : 889-***-****
Objective:
Aspiring for a promising and motivating career in a core company where my skills, knowledge and spirit for teamwork would be an asset.
Qualification:
Currently Pursuing M Tech 3rd semester in VLSI Design and Embedded Systems at Sapthagiri College of Engineering, Bangalore.
Course
Institution
University
Year of passing
Aggregate
M Tech
Sapthagiri College Of Engineering, Bangalore
VTU
2016
74.12% (1st sem)
BE
Gopalan College of Engineering and Management,Bangalore
VTU
2014
70%
Technical skills:
Languages known : C, Verilog, VHDL, Embedded C
Operating System : Linux, Windows.
Processor Architecture : 8051, 8086.
Interests:
Interested in VLSI Layout Design
Interested in working with integrated chips
Projects:
Layout Design:
Layout drawing of Inverter, NOR and NAND gates, Differential Amplifier
Cleaned DRC, LVS
Done PEX Checks for inverter
RTL coding:
RTL design of Synchronous, Asynchronous counter, D, SR, JK flip flops.
Also simulated these logic gates using Modelsim.
Median Filter Validation
HDL: Verilog.
EDA Tools: Modelsim, Xilinx ISE
My responsibilities included Implementation and validation of Median Filter on FPGA using Verilog. The objective of the project was to filter an image affected by impulse noise by passing it through a median filter. An input RGB image is converted into YCrCb format for efficient FPGA implementation.
A 3*3 Sliding Window technique has been used for sorting the pixel values of the image.
Technical seminar:
‘Design and Implementation of a Bi-directional Power Converter for Electric Vehicles with Charging feature’ – the Bi-directional cascaded Buck Boost converter implemented in Electric Vehicles helps to drive the dc motor using energy from battery and also recycles the energy through regenerative braking which is used to recharge the battery.
‘On Diagnosis of Timing Failures in Scan Architecture’ – deals with a methodology to identify the root cause of scan chain timing failures. The proposed work addresses the challenge of diagnosing multiple permanent or intermittent timing faults in scan chains, which closely approximates the realistic failure mechanisms observed in silicon.
Workshops:
Paper Presentation on ‘Eye Dialing’ –a practical approach towards attaining maximum security in case of high security zones where security breach is a concerning factor. It uses the concept of tracking the movement of the eye over the sequence of generated password and comparison to the base image for password matching.
Attended a 2 day workshop on Image and Video Processing conducted by Dr. Jharna Majumdar.
Achievements:
Secured 2nd position in Paper Presentation on Eye Dialing held in GCEM, Bangalore.
Secured 2nd position in Newspaper- Front Page Format Competition.
Certificate of Appreciation granted from Bangalore Association for Science Education for participating in Science-in-action held at Jawaharlal Nehru Planetarium, Bangalore.
Participated in INTACH (Indian National Trust for Arts and Cultural Heritage) Parampara, a heritage awareness program.
Extra Curriculum:
HP Award granted from the Governor of Karnataka, V.S. Rama Devi for The Bharat Scouts and Guides.
Have been granted the Proficiency Badge Certificates.
Certificate of Appreciation for participating in CMCA activities
Strengths:
Confidence
Good Communication Skills
Enthusiastic
Hard Working
Good team player and can work under pressure.
Able to handle multiple assignments
Personal Profile:
Name : Priyanka T N
Father’s Name : Nagendra Rao S N
DOB : 29/08/1992
Gender : Female
Languages known : Marathi, English, Kannada, Hindi.
Current Address : #5/1, 1st main, 1st stage, KHB colony, Basaveshwar Nagar, Bangalore
Marital status : Single
Nationality : Indian
Declaration:
Being to judge myself as a hardworking, ambitious and a capable team worker, I can contribute substantially to any venture or organization I join.
Place: Bangalore
(Priyanka T N)
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