VHDL, COMSOL

CURRICULUM VITAE

Name: Debalina Panda

Plot No.-*1, Gautam Nagar,

Bhubaneswar (Khordha), Odisha-751014

Mobile: +91-943*******

Email: ********.*****@*****.***

Objective:

To develop my skills and knowledge through hard work and creativity and contribute towards the growth of the Organization by using my knowledge and experience in the subject areas of Electronics and Telecommunication technology.

Educational Qualification:

Aug 2014- Till date Centurion University of Technology and Management Pursuing M.Tech in VLSI Design (final year)

M.Tech 1st year- 9.16 (CGPA)

July 2014 Utkal University

Passed Integrated Masters of Science in Electronics and Telecommunication with aggregate of 76.16%

May 2009 CBSE

Passed +2 Science (AISSCE) with aggregate of 74%

May 2007 CBSE

Passed 10th (AISSE) with aggregate of 79.2%

Skills:

Computer proficiency:

1. Microsoft Office

2. C

3. C++

4. Interface Certified Java Programming for Java 2 Platform 5. Acquainted with WIN 98/2000/ME/XP/7

Internship:

Summer VacationTraining-2012 in All India Radio & Doordarshan Projects undertaken:

1. Anti-sleep alarm circuit (Minor project)

2. Mobile based appliance control (Major project)

Personal information:

Name : Debalina Panda

Father’s Name : Sarbeswar Panda

Nationality : Indian

Date of Birth : 20th September 1991

Marital Status : Unmarried

Hobbies : Reading Novels, Art and craft, Internet browsing. Language(s) Known : English (proficient), Hindi (proficient) and Oriya (conversational) DECLARATION

Date:-

Place: -Bhubaneswar Signature.

I hereby declare that all the particulars given above are true to the best of my knowledge and belief.

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