fresher

NIKHILA ANN VARGHESE

Flat G-** Bala Sai Nivas, Abhaiah

Reddy layout, 4-B cross, Kaggadasapura :*******.********@*****.***

C V Raman nagar post, Bangalore- 560093 ph no: 964-***-****

Karnataka

OBJECTIVE

To work in a professional environment, where I am given the opportunity to passionately exploit my

knowledge to the fullest level of satisfaction both personally as well as for the institute I serve on the

whole.

EDUCATION

Course Discipline Institution Board/univers Year of Percentage/

ity CGPA

passing

M.Tech VLSI GITAM 2015

GITAM UNIVERSITY, 8.48

DESIGN HYDERABAD UNIVERSITY

B. Tech ECE JNTU 2012

Malla Reddy Engineering 79.46%

HYDERABAD

College, Medchal, Hyderabad

Intermediate MBPC CBSE 2008 80.8%

Kendriya Vidyalaya no.1

(10+2) stream Uppal, Hyderabad

Matriculation Kendriya Vidyalaya no.1 Uppal, CBSE 89.2%

2006

(SSC) Hyderabad

TECHNICAL SKILLS

Languages : C, VHDL

Tools : Cadence IC6.14, IC 5.141, Xilinx ISE 14.2, Tanner Tools 15.0

ACADEMIC PROJECT DETAILS

M. Tech Project:-

Title : Static power reduction in 32-bit ripple carry adder using dual threshold voltage assignment

Tools : Cadence Virtuoso IC 6.14

Description : In deep submicron CMOS technology leakage power is becoming a large part of total

power dissipation. The objective of the project is to judiciously use both low threshold

voltage and high threshold voltage so that there is no compromise on performance and at

the same time reduce the power dissipation.

B. Tech Project:-

Title : Design of 32bit Error Tolerant Adder

Tools : Xilinx ISE

Description : Error- tolerant adder used in digital signal processing systems that can tolerant certaiamount

of errors. ETA is able to ease the strict restriction on accuracy, and at the same time

achieve tremendous improvements in both the power consumption and speed performance.

MINI PROJECT:

Title : Adaptive Fuzzy Post Filtering using highly compressed videos

Tools : MATLAB

Description : A fuzzy filter adaptive to both sample’s activity and the relative position between samples

is proposed to reduce the artifacts in compressed multidimensional signals.

ACTIVITIES

Won 3rd place in quiz conducted by GLOBAL FOUNDRIES, organized by VLSI international

forum, national seminar on “VLSI Analog design, trends and challenges”, 2015

Attended two days workshop on “System on Chip (SOC) Design” in Muffakham Jah College of

Engineering and Technology.

Attended two days workshop on “Hands on training using LABVIEW SOFTWARE” in Malla

Reddy Engineering College

PERSONAL SKILLS

A quick learner and good communication skills.

PERSONAL DETAILS

Father’s Name : P. J. Varghese

3rd January 1991

Date of Birth :

Marital Status : Single

Sex : Female

Nationality : Indian

Languages Known : English, Hindi, Telugu and Malayalam.

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