Engineering Design

Abhijeet H. Deshmukh

Objective

To attain a challenging position in electronics hardware domain in an

interactive organization, providing learning opportunity.

Experience SUMMARY

. Fair knowledge of digital circuit design.

. Knowledge of ASIC/FPGA flow for Xilinx, Altera.

. Experience in debugging implemented projects and providing fixes for

the bugs.

. Documentation knowledge of writing Functional & Design Requirement

specifications.

. Participated as an instructor in ROBOCON- 2012.

. Presented paper in one international conference.

. Good Academic record since Diploma.

Personal Skills

. Ability to adapt quickly into work environment.

. Proactive with excellent problem solving skills.

. Ability to work independently or as part of a group.

. Good presentation / training imparting skills.

. Strong communication skills.

. Self Motivated & a good listener.

Technical Skills

Embedded : 8051, ARM7.

Embedded IDE : Keil ?Vision for 8051.

Debugging Tools : Logic Analyzer, MSO.

Languages : VHDL, Verilog.

VLSI Front End EDA tools: Xilinx 14.7, ModelSim.

educationAL DEtails

. M.E (VLSI & EMBEDDED SYSTEMS) from S.C.O.E (2012 - 2014).

. B.E (E & T C) from P.R.M.I.T & R, Pune with 2st Class (2008 - 2011).

. Diploma (E&TC) from Dr. Panjabrao Deshmukh Polytechnic, Amravati with

First Class (2005 - 2008).

. 10th from J.D. Chavare Vidyamandir Karanja (LAD) Pune board with 2nd

Class (2004 - 2005).

Project details

FPGA IMPLIMENTATION OF E1 TIME SPACE TIME SWITCH

Time Space Time Switch is fully synchronous System, Time switch is

basically interchange the time slot of the 8 samples at the delay of

125 sec, it minimize complexity of the links by using two Random Access

Memories.

For improving flexibility among the subscribers, another space stage is

added. The second space stage interchanges the time slot between the two

links.

Paper PRESENTATION

. Presented a paper on "FPGA Implementation of E1 Time Space Time

Switch" National Conference on Latest trends in Electronics and

Telecommunication, University of Pune, Sinhgad college of Engineering,

Pune,October 23-24,2013.

. Presented a paper on "FPGA Implementation of E1 Time Space Time

Switch" e-PGCON 2014, K. K. Wagh Institute of Engineering and

Technology, Pune, March 22-23, 2014.

area of interest

. I have knowledge of Digital system design, Timing issues in sequential

circuit's and its synchronization and I interested to work in RTL

design and its functional and timing verification.

Trainings

. Software Testing (Automated and Manual) in STQC, Pune.

Extra Curricular Activities

. Participated in the national level event in the ROBOTICS at

"PRAJWALAN-09" GCOEA Amravati

. Participated in the national level event in the Blind-Racing at

"Techno-Expert-10"PRMIT&R,Badnera, Amravati

. Participated in IEEE Communications Society Chapter of IEEE, Pune

section, presents Project Competition for M.E. Students (2013-14).

Personal Details

Date of Birth : 11th July 1989

Gender : Male

Marital Status : Single

Present address : Tejas Colony Bypass Road

Karanja (LAD)

Dist-Washim, Pin Code-444105

I hereby declare that the information furnished above is true to the best

of my knowledge.

Place: Pune

Date:

Abhijeet H Deshmukh

Mobile: +919*********

E-mail: **.********@*****.**

Contact this candidate