Test Cases Design
Resume:
GAURAV M. MORE
www.linkedin.com/in/gauravmore/ **************@*****.***
Career Objective
Seeking an ASIC/FPGA Design/Verification position that enables me to utilize my skills within the field to make a strong
contribution to the company.
Education
Master of Science, Electrical Engineering (Digital Design and ASIC/VLSI Design) GPA: 3.5/4.0
California State University, Long Beach - August 2013 - May 2015
Bachelor of Engineering (Electronics & Telecommunication) GPA: 3.6/4.0
University of Pune - August 2010 - May 2013
Diploma (Electronics & Telecommunication) GPA: 3.8/4.0
Maharashtra State Board of Technical Education - August 2007 - May 2010
Area of Specialization
ASIC/FPGA Design, Digital logic techniques, Formal Verification, SOC Verification, Synthesis, Place and route, Timing
and Power Analysis, Validation & Debug.
Technical Skills
Languages Verilog, System Verilog, VHDL, Tcl, Perl
Verification Tools Visual Studio, QSim, ModelSim, ISim, Prime time
Verification Methodologies OVM & UVM
Synthesis & Place and Route Tools Altera Quartus 2, Xilinx Vivado, ISE, LT Spice, Microwind
Programming Languages C, C++, Matlab, Lab VIEW
Hardware FPGA - Cyclone II, Artex 7, Spartan 3E, Spartan 6, Nexys 4, NI myRio
Assembly Language 8051
Professional Experience
FPGA Intern May 2013 – August 2013
Maharashtra Institute of Technology, Pune
- Worked on implementation I2C communication protocol and 16 by 16 Multiplier using Verilog code in Quartus 2.
- Emulated ASIC design on Altera Cyclone 2 FPGA & verified FPGA RTL by running block level test cases in ModelSim.
- Performed timing analysis using Prime Time and met timing constraints for the target device
- Generated FPGA verification flow through Tcl automation script.
Project Intern October 2012 – April 2013
Innovative Technologies, Pune
- Improved code coverage for speech to text converter in Mat Lab using Mel Frequency Ceptral Coefficient technique.
- Performed digital signal processing (DSP) on speech signal for signal modeling and pattern matching.
- Automated PIC 16F877 Microcontroller operation using programming on C for voice recognition technology for
automobile mounted devices.
VLSI Lab Assistant July 2012 – December 2012
University of Pune, Pune
- Assisted the professor in the research work in ASIC Design and Verification.
Technical Experience
Real-Time gender Detection on FPGA April 2015
- Implemented the algorithm on Mat lab using image processing to detect the gender on the person and developed
circuit on Lab view to support the algorithm on National Instrument’s myRio kit (FPGA & ARM Cortex-A9 processor).
ASIC Verification
Ethernet Verification using System Verilog May 2014
- Developed the test cases for verification of 2X2 Ethernet protocol using System Verilog (UVM Methodology). The
verification included generation of transaction, operational & analysis components in object oriented programming.
ASIC Boundary Scan Controller February 2014
- Implemented the Boundary Scan Controller using VHDL in Xilinx ISE for chip level verification for testing ASIC’s, 4-
wire interface interconnects. Timing analysis on data send over the IC between I/O, operated on Artex-7 FPGA board
ASIC Design using Verilog
16 bit RISC Processor October 2014
- Designed a 16 bit RISC general purpose processor in Verilog HDL. The Instruction Set Architecture draws inspiration
from the MIPS ISA and is reduced to fixed 16 bits per instruction. Verification of block level test cases on Test Bench.
DDR SDRAM Controller June 2014
- Developed a DDR SDRAM controller in Verilog on Altera’s Quartus 2. Supported data path width of 16, 32, and 64
bits with CAS latency of 2 to 3 clock cycle.
Embedded Development
Monitor and Control of Green House Environment May 2012
- Designed a RTOS to remote monitor and control the climate conditions to establishing correlation between sensors
signals and reference measurements, analyzing the growth and development of crops.
- Developed Assembly level code for AT89S52 Micro controller to execute the circuit on PCB.
Paper Publication
Real Time Gender Recognition on FPGA February 2015
International Journal of Science & Engineering Research (Volume 6, Issue 2, ISSN 2229-5518)
Certifications
OVM & UVM Test Benches February 2015
Udemy, California, USA (License Number - UC-6XXVF1C)
SOC Verification using System Verilog November 2014
Udemy, California, USA (License Number - UC-6X7BQJ8U)
Awards
Paper Presentation: Software Radio (SDR) and VLSI Chip December 2012
Techno Evolution, 2012 (Won second prize)
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