CURRICULUM VITAE
Mallikarjuna unnam
S/o Venkeswarlu
z.mekapadu (vill), Email id : ************.*******@*****.***
Ponnaluru (md), Mobile No : +91-944*******
Address for Correspondence:
Unnam mallikarjuna
S/o venkateswarlu
Door No:5-69,
Z.mekapadu(v),
Ponnaluru(m.d)
Prakasam(dt)
A.P .
Pin no 523111
Personal Data:
Date of Birth : 01 Jun 1993
Sex : male
Nationality : Indian
Marital Status : Single
Objective
Looking for a good career opportunity that enables me to improve my knowledge and skills, there by contributing the same for the growth of the organization
Academic Record
2010– 2014 Bachelor of Technology in
Electronics and Communication
Engineering in ABR college of
Engg&Tech,Kanigiri Affiliated
to J.N.T. University, Kakinada.
Percentage 65.32%
March 2010 Board of Intermediate Education
in SRI PRATIBHA Jr, college,
Ongole.
Percentage 79.2%
March 2008 Board of Secondary Education
In Vivekandha high school,
kandukuru .
Percentage 72.2%
Software Literacy
Languages : C basics, basic android
Operating System : windows operating systems
Graphic Suite : Adobe Photoshop
Languages Familiar:
Read : English, Telugu & Hindi
Write : English,Telugu &kannada
Speak : English & Telugu.
Personal Skills:
Energetic,
like to hard work,
Team work.
Hobbies:
Playing cricket,
Cooking foods.
Soft skills:-
I possess the required confidence in taking up new challenges and successfully completing it.
I have built up considerable interpersonal skills to coordinate work and liaise with various departments of an organization to get things done. I am adaptable, flexible and have the ability to manage pressure, ambiguity and change.
PROJECT DETAIL
TITLE:
DESIGN OF HIGH SPEED DDR3 SDRAM
CONTROLLER
DESCRIPTION,
The DDR3SDRAM controller is designed and it can interface with Look up table based Hash CAM circuit. Content-addressable memory (CAM) is a special type of computer memory used in certain very high speed searching applications. Because a CAM is designed to search its entire memory in a single operation, it is much faster than RAM in virtually all search applications. The architecture of DDR3SDRAM controller consists of Initialization fsm Command fsm, data path, bank control, clock counter, refresh counter, Address FIFO, command FIFO, Wdata FIFO and R_data reg
TEAM SIZE: 05
ROLE&RESPONSIBILITY:
Documentation &
Collecting the information
.
Achievements
Participated in cultural activities of my college .
Moreover I am the representative from my branch.
Declaration
All the details mentioned above are true and to the best of my knowledge. With above Skills I am looking for a suitable position at your esteemed organization.
Date:
Place :
U.MALLIKARJUNA