asic verification enganeer

RESUME

Ashok Kumar.G Email:******.****@*****.***

Ckb layout, munnekollala, Mobile: +91-855*******

Marahatalli,

Banglore

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and

Test benches in System Verilog.

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification

VLSI Domain Skills

HDLs: Verilog and VHDL

HVL: System Verilog

Verification Methodologies: Coverage Driven Verification Assertion Based Verification

TB Methodology: UVM

EDA Tool: Modelsim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis, ABV

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore

Year: June 2013

Bachelor of Technology, SITAMS College, Chittoor.

JNTUA University, Andrapradesh, India. Discipline: Electronics& Communications Engineering Percentage: 69.64% First Class. Year: May 2012.

Experience

Jan 2013– July 2013, Maven Silicon, VLSI Design and Training Center

VLSI Projects

Real Time Clock – RTL design and verification

HDL: Verilog

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Real Time Clock using Verilog HDL independently

Architected the class based verification environment using System Verilog

Verified the RTL model using System Verilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

Dual Port RAM – verification

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Dual Port Ram using Verilog HDL independently

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: UVM.

EDA Tools: Modelsim, Questa -- Verification Platform and ISE

Description: The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel0, channel1 and channel2.

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using UVM.

Verified the RTL model using UVM.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

DECLARATION:

I here by declare that all the above information provided by me is true to the best of my knowledge and belief.

Place:

Date:

G.Ashok kumar

Contact this candidate