Asic Design Verification Engineer
Resume:
VIDYA.K
ME VLSI Design
Contact No: 903-***-**** .
Email: ************.*@*****.***
CAREER OBJECTIVE
To work in an organization that will utilize and enhance my skill sets in the field of CMOS IC Circuit design, Layout and ASIC / FPGA design / Verification and applications.
BASIC ACADEMIC CREDENTIALS
Qualification
University/
Board
Institution
Period of study
Percentage of marks obtained
ME
(VLSI Design)
Anna University
K.P.R Institute of Engineering and Technology, Coimbatore.
2013-2015
8.41
(Upto III Semester)
B.Tech (Electronics and Communication Engineering)
University of Calicut
Jyothi Engineering College, Cheruthuruthy,
Thrissur.
2009-2013
7.67/10
Intermediate
State Board of Kerala
Vivekodayam Boys Higher Secondary School,
Thrissur.
2007-2009
91%
SSLC
State Board of Kerala
Holy Family Girls Higher Secondary School,
Thrissur.
2006-2007
90%
ACADEMIC PROJECTS:
ME Project (under progress) : Generation and Integration of Graph using TrekSoC for SPI Verification.
B.Tech Project:
Voice Recognition Robot [Team Size: 5]
Mini Project: Spy Ear [Team Size: 4]
SOFTWARE PROFICIENCY
Operating Systems : Linux, Windows Family.
VLSI Programming Languages : VHDL, Verilog HDL.
Layout Tools : Advanced Modelsim,Multisim,
Microwind.
VLSI Programming Tools : Xillinx 13.1
Languages : C, C++
Processors : 8085,8086.
AREA OF INTEREST
ASIC Design, RTL Design,
Physical Design and Verification.
FPGA Design
KNOWLEDGE AND EXPERIENCE
Knowledgeable in Perl Scripts.
Experienced in VHDL, Verilog, Xilinx Spartan FPGA programming.
Knowledgeable in UNIX Operating System.
Knowledgeable in CMOS VLSI design, Verilog RTL coding.
Knowledgeable in ASIC front end/back end design.
Knowledgeable in Physical design flow.
Knowledgeable in Simulation, Synthesis, MAP and Place & Route.
Expertise in development of IP Level Verification platform using System
Verilog/Verilog/Vhdl.
VLSI PROJECTS
Graph Based Verification of SPI Using TREK Software
Graph Based Verification of UART using TREK Software
Designed AMBA APB Slave using Verilog
PROFESSIONAL DEVELOPMENT
Presented a Paper on “Solid state device modelling and simulation” in KPR institute of engineering and technology, Coimbatore.
Presented a Paper entitled on “Low Power Parallel FIR Filter Design Using Symmetric Coefficient Fast FIR Algorithm”.
Submitted a Paper in International journal of Applied Engineering and Research on “Study of Graph Based SoC Verification.
STRENGTHS
A self starter with a Positive attitude.
Possessing good communication skills.
Flexible towards learning new concepts.
Strong desire towards achievement of Goals.
Desire to learn new technology to improve my skill set.
PERSONAL PROFILE
Father's name : Haridas.P
Mother's name : Valsala.R
Date of birth : 16-07-1991
Language known : English, Malayalam, Tamil, Hindi
Sex : Female
Marital status : Single
Nationality : Indian
Hobbies : Internet Browsing, Playing Shuttle, Reading Books,
Listening Music, Gardening.
Present Address : Plakkat House, Kuttenkulangara Lane,
Punkunnam P.O, Thrissur-680002.
DECLARATION
I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars.
Vidya.K
Place: Thrissur
Date: 08-06-2015
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