Design Engineer Project

AAKARAM NARESH Email : ******@*****.***

Mobile : +91-965*******

Career Objective:

To obtain a challenging and physical design engineer in a professional

organization, where I can contribute to the successful growth and to work as a team and

utilize the strengths of teamwork to achieve success

Professional Training:

Completed PG-Diploma course in VLSI PHYSICAL DESIGN from Institute of Shastra

Micro Systems, Hyderabad.

Professional skills:

Scripting Languages : Basics of Perl,TCL and Cshell Scripting.

Programming Languages : Basics of Verilog HDL and C Programming.

Operating Systems : Linux and Windows Operating Systems.

ASIC flow with emphasis on Physical Design

Has Good Knowledge in Floor Planning & Power Planning.

Good Placement by improving congestion and timing.

CTS building by meeting targets like skew and insertion delay.

Routing issues like cross talk and electro-migration.

Physical verification (DRC, ERC and LVS).

Good knowledge on Static Timing Analysis.

Basic knowledge on synthesis.

Good knowledge in Digital Design and CMOS Fundamentals.

EDA Tools:

Cadence First Encounter–Floor Planning, Place & Route, and clock tree synthesis,

Crosstalk Analysis & Power Analysis.

Cadence Rtl compiler logical synthesis.

Mentor Graphics-Modelsim, Xilinx ISE simulator.

Education Qualification:

Bachelor of Technology (Electronics & Communication) from Kite College of

Professional Engineering and Sciences (Affiliated to JNTU, Hyderabad) in 2014

with an Aggregate of 77.46%

Higher Secondary Certificate from Board of Intermediate Education, Sri Chaitanya

Junior College, Hydernagar, Hyderabad. in 2010, with an Aggregate of 85.1%

Secondary School Certificate from Board of Secondary Education, Sri Saraswathi

Shishu Mandir, Bandlaguda, Hyderabad. in 2008,with an Aggregate of 77.3%

Physical Design Project:

PROJECT 1 : (block level)

objective : Timing Driven Layout

Tools : SOC Encounter, QRC, ETS

Gate count / Area : 1296296(1.3M) / 6600998.49 um^2

Macros / STD Cells : 30 / 125195

No. of Clocks :7

Frequency : 200MHz

Utilization : 70.3%

Technology / Layers : TSMC 0.18 microns / 5 Metal Layers

Role : Netlist to GDS II - Floor planning, Placement, Clock Tree Synthesis, Routing, Timing

Closure, Static Timing Analysis, SI closure and physical verification.

Academic project:

Main Project: Development of the Highways Electronic Toll Collection and Entry

System with Alcohol detection system to avoid accident.

Description : In this work we are going to develop an embedded system board

attached with a RFID card reader and cards will be given to all the vehicle users. Driver

has to show his card while reaching to toll gate. The amount of that particular cost will be

deducted from the card. If no amount in the card there is a facility to recharge the card

at the toll gate itself. After the vehicles will be send to the alcohol test if there is any

sensing the gate will not be open the other way at parking gate will be open or other

condition when sensor has not sense road gate will be open.

Achievements:

Got 1st prize in circuit building at an event conducted in our college.

Extra Curricular Activities:

Participated in paper presentation and quiz competitions conducted at College &

University level. Presented Technical seminar "IRIDIUM SATELLITE SYSTEM (ISS)"

at my college.

Was an organizing member of the Technical Fest in my college.

Personal Profile:

Date of birth : December 8, 1992.

Sex : Male.

Nationality : Indian.

Marital Status : Single.

Languages : English, Hindi and Telugu

Permanent Address: H.No: 1-89, kondurgu village, mbnr district, Telengana state-

509207

Declaration:

I hereby declare that statements made are true and complete to the best of my

knowledge.

(Naresh)

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