Physical design engineer

RESUME

KRISHNA CHAITANYA Email:

******************@*****.***

Mobile:+91-720*******

Career objective

To be successful in the domain of VLSI by learning and implementing novel techniques as

a part of process refinement and would like to make positive contribution towards

promoting team spirit that adds value to the organization and to my professional growth as

well.

Academic qualifications

• M.Tech in VLSI Design with 7.46 CGPA from GITAM University, Visakhapatnam, AP, in

the year 2014

• B.Tech in Electronics and communication with 60.23% from AIET,Visakhapatnam,

affiliated to JNTU Kakinada, AP, in the year 2010

• Intermediate with 84.5% from Board of Intermediate education, AP, in the year 2006

• 10th Standard with 78.14% from Board of Secondary education, AP, in the year 2004

Work experience

• Worked for a period of ONE year at college level on EDA tools

• Trained in Physical Design for a period of 2 months in M.S.Ramaiah Institute of

Applied Sciences

Academic projects

Title: “Design planning of UART”

Technology/Layers : 65nm/9

Tools used : SOC Encounter

Standard cells : 836

Dominant Frequency : 500 MHz

Role&Description : Block level physical design

Brief description: Design was obtained from synthesis and finally gate level net-list

was obtained. The tasks handled were Floor-planning, Place & Route of the design. Power

optimization was performed in this design.

Title: “Design planning of USB”

Technology/Layers : 65nm/9

Tools used : SOC Encounter

Standard cells : 7176

Dominant Frequency : 500 MHz

Role&Description : Block level physical design

Brief description: The tasks performed were Floor planning, Place & Route of the

design. Clean DRC/LVS issues at block level.

Title: “Design planning of ALU”

Technology/Layers : 65nm/9

Tools used : SOC Encounter 11.1

Standard cells : 763

Dominant Frequency : 500 MHz

Role&Description : Block level physical design

Brief description: The tasks handled were Floor planning, Place & Route of the

design. Clean DRC/LVS issues at block level. Basically the block is congestion critical.

Title: “Design of Serial Peripheral interface”

Technology/Layers : 65nm/9

Tools used : SOC Encounter

Gate count : 1648

Dominant Frequency : 500 MHz

Role&Description : Block level physical design

Brief description: The tasks handled were Floor planning, Place & Route of the

design. The clock designed here will be used in remaining designs and will see that there

would be no timing violations. Parasitic capacitances were extracted.

Technical expertise

• Interested in Physical design

• Worked on 65nm,90nm,180nm technologies for a period of 8 months on CADENCE

tools at college level

• Synthesizing the design to derive the gate level net-list of several designs with different

effort levels

• Generation parasitic resistance and capacitance values from SPEF

• Generating macro libraries

• Minimizing set up and hold delays by adding buffers at capture and launch paths

respectively

• Hands on experience in Synthesis

• Proficient in CADENCE Schematic editor, SoC Encounter 11.1

• Can understand Physical design back end flow from floor planning, power planning,

placement, CTS, routing and verification(LVS,DRC)

• Inquisitive in nature and have a desire to understand how things work

• Good personal organization with effective prioritization and time management skills

• Able to maintain focus and to see tasks through to timely completion

Personal information

• Father’s Name: Shri. Vijaya ram

• Date of Birth: June 10,1988

• Passport no: H7510335

• Languages known : Telugu, English and Hindi

• Hobbies: Poetry, Traveling and Listening to music

• Mailing address: 13th cross, S. Ramaiah layout, T.Dasarahalli, Bangalore-560057

Declaration

I have furnished my academic career details, along with my personal details which are true

to best of my knowledge.

Sincerely,

PLACE: Bangalore

(V.K.Chaitanya)

Krishna

chaitanyaVelamuri

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