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Engineering High School

Location:
India
Posted:
February 17, 2015

Contact this candidate

Resume:

RESUME

MURALI.S

*/**,****** *****,

Regadahalli(Po),

Pappireddipati (Tk),

Dharmapuri (Dt),

Pin-635301.

E-mail : *************@*****.***

Mobile no : 811*******

OBJECTIVE

To work in a firm with a professional work driven environment where I can utilize and apply

my knowledge, skills which would enable me as a fresh graduate to grow while fulfilling

organizational.

goals.ACADEMIC QUALIFICATION

Master of Engineering in Applied Electronics

Aksheyaa College of Engineering, Anna University, Puludivakkam.

Obtained – 7.4(CGPA) (Still 3rd semester).

Bachelor of Engineering in Electronics and Communication Engineering

Aksheyaa College of Engineering, Anna University, Puludivakkam.

Obtained First Class – 7.1 (CGPA) - April 2013.

Higher Secondary Course Certificate

A.M.G Matric Hr Sec School, B.Nadoor

Obtained - 88% - March 2009.

Secondary School Leaving Certificate

A.A.Goverment High School, Kotapatty.

Obtained – 88.8% - March 2007.

SOFTWARE SKILLS

Language : Basics of VLSI, Networking, C, C++

PG PROJECT

Title : Fuzzy Clustering for segmenting Brain Tumors based on LIPC

Platform : Digital Image Processing

Software used : Matlab

Description : The project proposes a segmenting tumor by using spatial fuzzy clustering

algorithm for Magnetic Resonance images(MRI) to detect the Brain Tumor. Since LIPC algorithm is

gives only 84% of clarity so we additionally adding fuzzy clustering. This algorithm have been

widely studied and applied in a variety of substantial areas.

UG PROJECT

Title :Designing of Efficient Arithmetic Unit based on Vedic Mathematics

Code Developed In : Verilog HDL

Software used : Xilinx

Description : Ancient Indian Vedic Mathematics has a unique technique of calculations based

on 16 Sutras and 13 sub sutras. Employing these techniques in the computation algorithms of the

coprocessor will reduce the complexity, execution time and area etc. The proposed Arithmetic unit is

coded in Verilog HDL, simulated, synthesized and implemented by using Spartan 3E FPGA.

INDUSTRIAL VISIT

BSNL – Regional Telecom Training Centre.

TRAINING

IBM Career Education Program

Course Name : Rational Testing fundamentals

Technology Used : IBM Rational Functional Tester & IBM Rational Quality

Manager

NIIT

Course Name : Employability Enhancement Program

ACHEIVEMENTS

Selected inter-zonal kabaddi player in college level.

One of the Anti Ragging committee Member in my college.

PAPER PRESENTED

Participated in “National Conference on Communication Convergence – 2K11” in Aksheyaa

College of engineering on 20th August 2011.

Presented a paper “Designing of Efficient Arithmetic Unit Bobased on Vedic

Mathematics” the 1st National level technical symposium conducted in ARM College of

engineering.

Participated in “Entrepreneurship Orientation Programme” (NSIC) Workshop conducted in

“Aksheyaa College of Engineering” on 16thAugest 2012.

PERSONAL INFORMATION

: 5th June 1992

Date of Birth

Gender : Male

Father name : Mr.A.Sundararajan

Mother tongue : Tamil

Nationality : Indian

Marital Status : Single

Languages : Tamil,English,Telugu

Hobbies : Playing games (Kabbadi, Volley Ball)

Permanent address : 2/66,Mullai Nagar,

Regadahalli(Po),

Pappireddipati (Tk),

Dharmapuri (Dt),

Pin-635301.

DECLARATION

I do hereby declare that the particulars of information and facts stated herein

above are true, correct and complete to the best of my knowledge and belief.

Date :

Place : MURALI S



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