NIDHI SHARMA
Flat no. G*, New Heaven Apartment, Nationality: Indian
Outer Ring Road – Whitefield Bypass road, Age: 29 years
Doddenakundi, Telephone: +919*********
Bangalore- 560037,
Karnataka, India.
Mobile number: +919*********
Email: ***************@*****.**
Career Overview
Results-driven SoC/ASIC Functional Verification Methodology Engineer with vast experience in Functional
verification for ARM based SoC, Development of Verification Plan, VMM based Verification Environment,
Assertion Based Verification, Low Power Verification, Development and deployment of Test Bench
Qualification Methodology(Certitude), OVM methodology Design flow expertise in Functional Verification
Automation with Perl/Tcl Scripts and Makefile for various applications. Well conserved with HVL based
languages such as Specman & System Verilog.
Core Strengths
Management experience in building team from scratch, motivating and managing to develop new
methodology in Functional Verification
Managing team interaction and facilitated cross-site collaboration to ensure information is widely spread
Managing customer interface
Optimizing verification time by automating things wherever required
Technical Proficiency
Languages System Verilog Assertion, VHDL, Verilog
Knowledge VMM, OVM, Testbench Qualification, Low Power Management (UPF), Assertion
based Verification, Property checking
Tools MVSIM, MVRC, Certitude, Questasim/Modelsim, Onespin(Formal Verification),
Verdi (Debugging)
Revision Control Clear Case, Design Sync
Scripting Python, Perl, Makefile,Tcl
Growth Path
Designation Company Period
Sr. Design Engineer FSL Freescale Semiconductors June 2013 – Present
Sr. Design Engineer II Infineon Technologies March 2008 – June 2013
Educational Qualifications
2007- 2008 PG Diploma (VLSI Design) Sandeepani School of VLSI Design, Bangalore
2003- 2007 B.Tech (Electronics & Communication) from UPTU, Lucknow
Major Achievements and Awards
Paper at SNUG 2013 (Bangalore) on Testbench Qualification
Won in poster presentation for Innovation for Automatic generation of Assertions for Low power
Verification
Delivered seminar on power aware simulation using Questasim.
Proposed Innovation topic on automating the UPF (Unified Power Format) generation
Won in COGNIZANCE 2005-2006(Technical fest of IIT Roorkee) in KINTOP (Model making contest
prepared model of aerodynamic wind tunnel).
Won third place in Paper Presentation on G.P.R.S in SOFTKORN
Key Projects Accomplished
The details of the various assignments that I have handled are listed here, in reverse chronological order:
Project: Verification of ARM Based SoC LS2 (Layerscape Architecture) Company: Freescale Semiconductors
Responsibilities:
IO Vérification, Low power Vérification
Assertion Based Verification.
Development of test case in System Verilog and C.
VMM based verification Environment.
Gate level simulation.
Testcase development on Cadence Palladium environment.
Test pattern support for assigned modules.
Post Si Validation of EPU & Debug module in SoC.
Project: Testbench Qualification (Certitude stuck at fault methodology) Company: Infineon Technologies
Responsibilities:
Successfully Developed (from concept to implementation) Certitude stuck at fault methodology
Mentor/Motivate team to develop the methodology
Rolled out to IPM and VV group the stuck at fault methodology for certitude and improve the coverage
Actively involved in client interaction.
Project: Functional Vérification of I2C (Specman) Company: Infineon Technologies
Responsibilities:
Successfully Completed the Functional Coverage (100%) with Specman & Certitude stuck at fault methodology
Actively involved in client interaction.
Project: CCS Switch-off Concept (Low Power Vérification) Company: Infineon Technologies
Responsibilities:
Developed and Deployed the verification methodology for the new switch off concept
Low power gate level simulation.
Qualifying on Pilot Projects
Rollout of automatic assertions for low power
Actively involved in client interaction.
Company: Infineon Technologies.
Project: System Verilog (OVM), UPF, Debugging Support
Responsibilities:
Specification development.
Implementing the complete subflow integration (Perl) for simulation flow-package.
Development of testcase
Qualifying on Pilot Projects
Actively involved in client interaction.
Project: Functional Verification Design Flow Development Company: Infineon Technologies
Responsibilities:
Updated and executed test suite for Various Design Flow releases and Enhanced regression
Automation scripts for simulation, onespin subflows
Evaluation of tools(debugging features supports in Modelsim ) part of vender consolidation
Adding new features to Design Flow. Developing methodology for them
Other Details
Date of Birth : 8th April 1986
Marital Status : Married
Languages Known : Hindi, English
Passport No. : E1752907