Engineer Project

GAURAV KUMAR GUPTA

PSR PG beside MVJ international school marathahalli Bangalore-37

Mob : +91-805*******

E-mail : **********@*****.***

Seeking Entry Level Assignment as Verification Engineer/VLSI Design with Growth Oriented

Organization

SUMMARY OF SKILLS

Currently working as an ASIC Design Verification Trainee Engineer at CVC PVT LTD Bangalore from July 2014 to till

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date.

I have Qualified B.E. in 2013 from Govt. Engineering College Bilaspur Chhattisgarh.

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Achieved the Scholarship from AICTE according to tuition waiver scheme (TWE).

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Strong Knowledge on Computer Programming, Languages like C, C++ and Core Java.

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Well Worse with Digital Electronics, Computer Network.

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Quick learner and Self Directed, Consistent updating self with the emerging trends in the Industry.

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An efficient key player in challenging and creative environment with excellent capacity to adapt to new technology and skills.

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Possesses strong management, communication & interpersonal, problem solving skills.

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TECHNICAL SKILLS

HDL Verilog

HVDL LANGUAGES System Verilog, SVA(System Verilog Assertion)

VERIFICATION METHODOLOGY Universal Verification Methodology(UVM)

SCRIPTING LANGUAGE Perl

PROGRAMMING LANGUAGES C,C++

VLSI SIMULATION TOOLS Questasim, Modelsim, Riviera Pro, ModelSim 6.5

VLSI SYNTHESIS TOOLS Quartus, Xilinx ISE 9.1I

OPERATING SYSTEM Windows,Linux

PROFESSIONAL EXPERINCE

Since July 2014 to till date at CVC PVT LTD

PROJECTS:

1. Verification of APB-SPI UVC Using UVM

Role: Implemented and developed test bench environment and done the entire project.

Tools Used: Questa Sim and Riviera-Pro tool.

Description: Understanding the basic read and writes protocol. Create Constraint Random Verification environment

And architecture verification plan create all agent components from the scratch, integrate and write the

sequence. APB_MASTER connect SPI_MASTER with the help of APB Wishbone Bridge. APB_MASTER

initiate the transfer send the SPI_MASTER. SPI_MASTER drive the SPI_SLAVE. All the TB_TOP and connect

with TOP_DUT MC Design was verified with UVM using Questa tool.

2. Verification of Memory Controller using System Verilog

Role: Implemented and developed test bench environment and done the entire project.

Tools Used: Questa Sim and Riviera-Pro tool.

Description: The Memory controller operation performs Write into and Read from the memory. MC design was verified with

UVM using Questa tool.

3. Verification of FIFO using UVM

Role: Implemented and developed test bench environment and done the entire project.

Tools Used: Questa Sim and Riviera-Pro tool.

Description: Synchronous FIFO with push_on_full_error and pop_on_empty_error.

FIFO design

was verified with UVM using Riviera-Pro tool.

4. Verification of UP-DOWN COUNTER using System Verilog

Role: Implemented and developed test bench environment and done the entire project.

Tools Used: Questa Sim and Riviera -Pro tool.

Description: UP-DOWN COUNTER with Terminal Count UP- DOWN COUNTER design was verified using System

Verilog verification language using Questa tool.

5. Verification of S2P using UVM

Role: Implemented and developed test bench environment and done the entire project.

Tools Used: Questa Sim and Riviera-Pro tool.

Description: S2P (Serial-to-parallel) converts stream of data into packets. DUT captures data till the occurrence of

EOP (end of packet). S2P design was verified with UVM using Questa tool.

EDUCATIONAL QUALIFICATION

Qualification School/College University/Board Year Specialization Score

Chhattisgarh Swami

Govt. Engineering Vivekanand Information

B.E. 2013 62.14%

College Bilaspur Technical University Technology

Bhilai

Govt. Multipurpose Physics,

Class 12 Higher Sec. School CGBSE 2008 Chemistry, 65.80%

Pendra Math

PERSONAL DETAILS

Date of Birth 29-06-1990

Sex Male

Marital Status Single

Nationality Indian

Languages known Hindi, English

Father's Name Avneesh Gupta

Permanent Address Neha Bangle Store, Girls School Road Pendra

Dist.-Bilaspur CHHATTISGARGH PIN-495119

Phone No 91-805*******

DECLARATION

I hereby declare that the above-mentioned information is correct up to my knowledge.

(Gaurav Kumar Gupta)

Contact this candidate