Engineer Project

CAREER OBJECTIVE

PRADIBHA.V

To synergize all my strengths and resources available to

work with complete perfection and professionalism.

Contact Address: To become a virtuous in each and every work by showing

No:9,Dreamz DevanaiAppt, diligence and thus continuously improving the

East Ranganathapuram organization and myself.

Srirangam.

Pin code: 620006

ACADEMIC CHRONICLE

:991-***-**** B.E (ECE) (2013) : 7.1(CGPA)

M.A.M College Of Engineering

Email: ************@*****.*** Trichy

HSC (2009) : 69%

A.R.K HIGHER SECONDARY SCHOOL

Trichy (D.T).

Personal Memorandum :

SSLC(2007) : 68%

Date of Birth : 21.05.1991 R.S.K Higher SecondarySchool.

Trichy (D.T).

Sex :Female

TECHNICAL SKILLS

Marital Status : Single

Languages : C, C++, HTML.

Nationality : Indian

ADJP

PEARL Scripting Language

FIELD OF INTEREST

DIGITAL ELECTRONICS.

Languages Known:

VLSI.

Tamil

FPGA

English

Kannadam

RTL design

Verilog

PROJECT

Design of dynamic partial reconfigurable FIR filter

architecture for DSP applications

MINI PROJECT

Simple Code Locking System.

Family Background: Robotics.

Running LED display

Fathers’ Name :

Speed control for highways

Mr. N.Venkatraman

Occupation :

Computer Operator

PROJECTS AND TRAINING EXPERIENCE

Mothers’ Name:

Mrs. V.Jayashree

Occupation : Underwent an In-plant training in BSNL & ALL INDIA

Home maker RADIO for one week.

Attended Workshop on PCB DESIDNING AND

LAYOUT conducted by ACOEL.

Attended A NATIONAL LEVEL ROBOTICS

WORKSHOP organized by ORANGE RESEARCH

LABS and CENTER OF ROBOTICS AND ARTIFICIAL

Hobbies

INTELLIGENCE(CRAI)

Undergone workshop in Embedded and Networking

Singing

conducted by EZONE,Tiruchirappalli.

CAREER HIGHLIGHTS

Sion Semiconduntor as Engineering Intern

January 2014-till date

Responsibilities

Understanding the overall design, preparing a

verification plan, create test-benches, debug

verification results, create automation for

verification

Performed the tasks of implementing stimulus and

checking modules with the help of senior

verification engineer

Handled responsibilities of preparing and

implementing detailed test plans for design

modules

Project Details:

RTL of UART and I2C using Verilog

Verification of Ethernet protocol implementation

using System Verilog

PERSONAL STRENGTHS

Highly organized and dedicated with a positive attitude.

Have good oral and Interpersonal communication skills.

Good grasping skills, self motivated and willingness to

learn.

REFERENCES

Dr.J.Wiliam,M.Tech.,Ph.D.,

The Head of the Department,

Electronics and Communication Department,

M.A.M.College of Engineering,

Siruganur, Trichy-621 105.

DECLARATION

I hereby declare that the above mentioned statements are

true to the best of my knowledge and belief.

(PRADIBHA.V)

Contact this candidate