Design Power
Resume:
RAHUL KAUSHIK
**** ********* **** #***, **********, TX 75080 Mobile: 469-***-**** Email: *****.*******@********.***
LINKEDIN Profile: www.linkedin.com/pub/rahul-kaushik/20/260/269/
ACADEMICS
The University of Texas at Dallas, Richardson, TX May 2014
Master of Science – Electrical Engineering (Circuits and System) GPA: 3.5/4
Institute Of Technology, Nirma University, Ahmedabad, INDIA June 2010
Bachelor of Technology –Instrumentation & Control Engineering GPA: 9/10
RELEVANT COURSES
VLSI Design Analog IC Design Advanced Digital Semiconductor Power Management
Logic Processing Technology Integrated circuits
RF Integrated circuits Energy Harvesting, Testing and Testability Linear Systems ASIC Design
Storage and Powering
WORK EXPERIENCE
Power Electronics Lab, UT Dallas August 2013- Present
Student Research Assistant
Test bench setup and verification of Power Supplies.
Schematic and PCB design for DC-DC converter, DC-AC inverter.
DSP programming and closed loop regulation of power converters
FREESCALE Semiconductor Inc. Austin
Product Engineering Intern May 2013- Aug 2013
Characterization and statistical analysis of semiconductor chips using JMP tool.
Development of JMP Scripting Language based scripts for automating the characterization process
Worked on Automatic Test Equipment (Teradyne J750) for semiconductor Testing, Learned about ATE, handler, Test Process and Test
Programming for ATE.
Bench validation of semiconductor chips.
Larsen & Toubro Ltd. Faridabad, India August 2010-July 2012
Graduate Engineer
Test bench setup and verification of Power Supplies.
Bench Verification of ADC, DAC & PLL.
PCB layout and Design of Power Converters and analog circuits.
Microcontroller testing and application Programming.
ACADEMIC PROJECTS
10 bit pipelined Analog to Digital converter
10 bit pipelined Analog to Digital converter (ADC) with 400MS/s conversion speed in CMOS 0.35um process
2V peak to peak full scale voltage, 58db SNR, ENOB 9.1, SFDR 70dB.
High swing fully differential telescopic operation amplifier with gain 60db.
Clock bootstrapped switches and switch capacitor circuit incorporated.
Portable LDO design
Design of low Voltage LDO regulator for Portable Applications in CMOS 0.35um process.
Use of voltage buffer and shunt feedback control for stability
Operating voltage 2V, dropout 0.2V, maximum load current 150mA, quiescent current 40uA and settling time less than 40usec.
PLL Design
PLL (Phase Lock Loop) designed as frequency synthesizer in CMOS 0.18um Process.
Operating range from 200MHz to 440MHz.
Simulation Testing on Cadence and then actual testing on chip after fabrication.
PV based harvesters (solar) for Wireless sensor nodes
Design of efficient power management circuit to wireless sensors in building environment with autonomous and sustainable power.
Input power range from 5μW-to -10mW, input Voltage range from 0.7V to 2V, output range from 0.2V to 3.3V.
Optimized the design for the given specifications with higher efficiency and MPP algorithm for Maximum Power transfer.
DC-DC Converter
Design of PWM buck SMPC with control strategy and stability compensation using TSMC 0.35um process.
Input supply of 3.3V, Regulated output 1.8V
Output regulation and transient response of less than 100μsec for load changes and analyze the design for Power efficiency.
Also Design of low power closed loop SCPC with load change transient response of less than 25μsecs.
DSP & Microcontroller based Power management Applications
Use of C2000 microcontroller for generating PWM pulses in a closed loop control application.
Implementation of the dead time compensation algorithm using DSP.
Design of 2-stage Operational Amplifier
Design of two stage differential input and single ended output amplifier using CADENCE Design Suite.
Optimized the design for the given specifications such as differential gain, CMRR, Slew Rate, Power Dissipation etc.
RF System Receiver Design for LTE
Designed and simulated a Direct Conversion Receiver (DCR) front end for 4G wireless system for LTE Band 1 Rx frequency of 2110-2170
MHz in IBM 180nm RFCMOS process.
Designed the individual blocks such as LNA, Mixer and VCO to meet the chosen criteria in addition to the system le vel Link Budget
Analysis. The simulations were done with Agilent Advanced Design System (ADS).
Low Noise Amplifier Design
Two stage Low Noise Amplifier Design using Agilent ADS tool in IBM RFCMOS 180nm process.
Common source cascade topology, high gain and low noise figure.
Noise figure 3dB, gain 22.76dB,IIP3 8dbm, current consumption less than 3mA, operating frequency 5GHz
ALU IC Design Using Cadence Design Suite
Designed a 32-bit ALU using Cadence tool.
Designed a standard cell Library.
Design involved running DRC, LVS, QRC Extraction, HSpice Simulation, Place & Route using Encounter and timing analysis using
Primetime.
Test Pattern Generation and Fault Analysis
Use of Tetramax tool to model the Digital circuits and analyzing all stuck at Faults and Test Pattern generation.
Using Tetramax Tool generating 8 bit pseudorandom Test pattern for BIST applications.
64 bit double precision complex number floating point butterfly FFT block
Use of IEEE 754 standard for computing addition and multiplication
Optimization with two flag interface pipelining at 300Mhz.
Includes RTL coding, synthesis, logic and timing verification, gate level simulations, placement and routing.
SKILLS
IC Design Tool- Cadence Design Suite, Cadence Virtuoso Layout Editor, Synopsys Design Vision, Agilent ADS, PrimeTime, Cadence
Encounter, Tetramax Synopsys.
PCB Design Tool- Cadence Orcad, Altium
Simulation Tool – Synopsys Hspice, MATLAB, LABVIEW, ModelSim, PowerSim, Code Composer Studio (CCS), Xilinx ISE
Programming Languages – C, C++, Assembly Language Programming, Unix, VHDL, Verilog, Verilog-ASM, System Verilog, Visual
Basic, Perl, JSL (JMP Scripting Language),
Lab Equipment– Oscilloscopes, Spectrum analyzer, Power supplies, Multimeter, Logic Analyzers
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