Project High School

NILEENA ROMEO

PHONE NO: 048*-*******

MOBILE : 984-***-****

EMAIL :**************@*****.***

CAREER OBJECTIVE

Seeking challenging career in good organization with committed and dedicated people were I can project my

potential and help the organization to restore its goals .

ACADEMICS

SL.NO PERIOD COURSE INSTITUTION BOARD/

OF UNIVERSITY PERCENTAGE

STUDY 1. 2012- MTech (VLSI & Adi Sankara Institute of MG University -

2014 Embedded Engineering & Technology Kottayam 7.6 CGPA[sem

Systems) Kalady 1]

2. 2011- PG DIPLOMA National Institute of A Grade

-

2012 in ASIC Electronic & Information

DESIGN & Technology,NIT Campus

VERIFICATION Calicut

3. 2007- B.E Jayamatha Engineering Anna

2011 (ECE) College,Nagercoil,TamilNadu University,

Tirunelveli 79.00%

4. 2005- XII Chavara Public School,Pala Central Board

2007 of Secondary 75.00%

Education

5. 2004- X Sobhana English Medium Kerala State

2005 High School Board 91.50%

Kothamangalam

.

TECHNICAL SKILLS:

Good Knowledge in Digital Logic Design.

Good programming skills using Verilog HDL and VHDL .

Good Programming knowledge in C, C++ and System Verilog.

Good Knowledge in ASIC Verification Methodologies VMM and OVM.

Good Knowledge in Coverage and Assertion based Verification.

Good knowledge in Xilinx FPGA Architectures.

RTL Core design and development using Verilog HDL and VHDL for ASIC and FPGA Designs .

Writing Simulation and Synthesis scripts using Tcl and Perl.

Functional Verificat ion using Synopsys VCS,Questasim and Modelsim.

Analog designing using Cadence Virtuoso and digital designing using Cadence Incisive tool.

ASIC Synthesis and Timing Analysis using Synopsys Design Compiler .

FPGA Synthesis using Xilinx ISE and ALTERA Quartus2.

PROJECTS:

PROJECT TITLE : Design and Verification of Memory Module

Tools : Synopsis VCS, Synopsis DC, Unix Shell Scripting

Description:

The objective of the project is to design a 1024x8 memory module, write test cases and test automation usin g

script. The test cases like address test and data test is written and verified.

PROJECT TITLE : Design and Verification of FIFO

Tools : Synopsis VCS, Synopsis DC, Unix Shell Scripting

Description:

The objective of the project is to design a 16x8 FIFO module, write test cases, assertions and test automation

using script. The various test cases were written and integrated with test environment for automated testing, functional

and code coverage. The coverage reports were generated and analyzed.

PROJECT TITLE : RISC CPU Core

Tools : Modelsim,Synopsis VCS

Description:

The objective of the project is to analyse various modules in RISC CPU Core. The verilog files have been given

and the RISC CPU Architecture is traced from the verilog files. All the files has been integrated and simulated in

modelsim and Synopsis DC tools.

PROJECT TITLE : Synthesis and Timing Analysis of RISC CPU Core

Technology : TSMC 65nm

Tools : Synopsis DC, TEL Script

Description:

The object ive of the project is to synthesis RISC CPU Core. TCL Script file has been written for automated

synthesis of CPU Core. Various synthesis reports were generated and analyzed the area, power and frequency.

: System Verilog Based Verification of Packet Router

PROJECT TITLE

Tools : Synopsis VCS, Questasim,PERL Script

Description:

The objective of the project is to create various verification components and verification environment by

integrating DUT and Verification components. The various test cases were written and automated by writing PERL

Script. The verification is OOP (Object Oriented Programming) based Verification and System Verilog is used to create

the Verification environment. The coverage is also analyzed for various test cases.

PROJECT TITLE : FPGA Synthesis of RISC CPU Core

Technology : ALTERA/Xilinx FPGAs

Tools : Quartus2/Xilinx ISE, Altera Signal Tap Analyzer

Description:

The objective of the project is to synthesis RISC CPU Core for FPGA platform. Various modules are in tegrated

and synthesized. Synthesis reports have been analyzed for r esource utilization and timing.

PROJECT TITLE : I2C Design and Implementation Using VHDL

Organization : Keltron Infotech, Cochin,Kerala

Team size :4

Duration : 4 Months

: Modelsim,Xilinx ISE

Tools

Master Thesis :A Resource Efficient hough Transform for Real time applications

The thesis aims at developing a hough transform which is used to detect straight lines in real time images which

can be used in motion detection systems.The hardware implementation to be done in a FPGA.

Personal Traits

Creativity, balanced learning ability and skills.

Ability to learn from mistakes

Good observer and listening skills

Ability to communicate effectively

INTERESTS

Reading books

Dancing

Singing

ACHIEVMENTS

Won prizes in ‘work experience‘ in school and district levels.

Won prizes in dance competitions in school and college levels.

Done paper presentations in symposiums held at college level.

PERSONAL DETAILS

NAME : NILEENA ROMEO

FATHERS NAME : ROMEO JOSEPH

AGE & DATE OF BIRTH :24, 05-04-1989

RELIGION & CASTE :CHRISTIAN,ROMAN CATHOLIC SYRIAN CHRISTIAN

LANGUAGES KNOWN : ENGLISH,MALAYALAM, HINDI

NATIONALITY : INDIAN

ADDRESS FOR COMMUNICATION : OLIAPURAM HOUSE

KOTHAMANGALAM P.O

ERNAKULAM DIST.

KERALA

PIN:686691

DECLARATION

I hereby declare that all the details furnished above are true to the best of my knowledge.

Place: Kothamangalam

Date: 14-04-2014 NILEENA ROMEO

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