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engineering.BE:ECE.ME:VLSI DESIGN

Location:
India
Salary:
20000
Posted:
June 26, 2014

Contact this candidate

Resume:

JEENA JOY

*********@*****.***

+917*********

+91-812*******

OBJECTIVE

I would always strive for the growth of the company. My Goal is to work with Latest

Technologies and Professional group where my Skills and Knowledge can contribute to its success.

ACADEMIC PROFILE

YEAR OF

QUALIFICATION INSTITUTION BOARD/UNIVERSITY PERCENTAGE

PASSING

Vivekanandha college of

ME-VLSI design 73

Engineering for Women Anna University Chennai 2014

Tiruchengode.

Sasurie Academy of

Engineering,

BE-ECE Anna University Chennai 2012 80

Kariyampalayam.

Coimbatore.

Baker Memorial Girls

HSC higher Secondary State board 2008 78

School,kottayam

Baker Memorial Girls

SSLC higher Secondary State board 2006 81

School,kottayam

TECHNICAL SKILLS

Softwares known : MS office, Xilinx ISE, Modelsim,Tanner EDA, Matlab

Programming languages known

Hardware description : VHDL,Verilog HDL

software : C,C++

: Windows 98, XP, Vista, 7

Platforms used

AREA OF INTEREST

VLSI design

Digital electronics.

Optical communication.

SOFT SKILLS

Patience.

Team worker

Problem solving abilities

verbal and written communication skills

willingness to learn more.

ACHIEVEMENTS

Excellent academic background with minimum first class in all the courses pursued with

percentage closer to or higher than distinction.

Published a paper entitled “Low power digital design using Asynchronous fine grain Logic “in

IJAICT,volume1.issue 2.june2014.

Attended an IEEE International conference on “Low power digital design using Asynchronous

adaibatic Logic “ in J.K.K Nattraja college of engineering and technology.

Attented an International conference on “Low power digital design using Asynchronous fine

grain Logic “ in EASA college of Engineering.

National conference ” Recent advances in Science,Engineering and Technology RASET ” on “

Low power digital design using Asynchronous Adaibatic Logic “ in Jay Shriram college of

Technology Tirupur.

Attended a workshop on”VLSI design-Tanner EDA Tool”.

Attended a seminar on “Java technology”.

Attended a Workshop on” Embedded system”.

Attended a two day workshop in” Ethical Hacking and Information Security” .

Attended a two day workshop about “DIP using MATLAB Implant training in “V-GUARD”

Industries ltd.

EXTRA CURRICULAR ACTIVITIES

Won prizes in Instrument music and various culturals during the school and college level

competitions.

Participated in Combined Annual Training Camp of” Nationl Cadet Crops”.

IEEE student member.

PROJECT UNDERTAKEN

Main project (BE): Towards Power Line Communication In Vehicle.

My BE project is based on the Power Line Communication instead of CAN so as to reduce wire length

and ensure minimum noise interference in communication.

Main project (ME) :Low power digital design using Asynchronous Fine Grain Logic.

That is based on an innovative way to reduce power consumption by low-power logic family, called

asynchronous fine-grain power-gated logic (AFPL).

PERSONAL DETAILS

Father’s Name : C.Joy

Mother’s Name : Chinnamma Joy

Date of Birth : 17-10-1990

Gender : Female.

Permanent address : carackattu(h)

Mallosserry p.o

kottayam

Marital status : Single.

Languages Known :

To Speak : Malayalam, English,Hindi and Tamil

2

To Read : Malayalam, English and Hindi

To Write : Malayalam, English and Hindi

Hobbies : Playing keyboard. Surfing internet.

REFERENCE

1.Mr.S.Sakthivel. 2. Ms..V.Vandhana,

Assistant Professor. Assistant Professor,

Dept of Electronics and Communication Dept of Electronics and Communication

Engineering Engineering

Vivekanandha college of Engineering for Sasurie Academy of Engineering

Women Coimbatore.

Tiruchengode ph:984-***-****

Ph:975*******

DECLARATION

I here by declare that the above furnished informations are generic to the best of my

knowledge.

Date : 08.06.14

Place :kottayam JEENA JOY



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