Verilog, System verilog, UVM, ASIC design and verification.

TAUSIF A SHAHAPURI

Tel: +91-988*******(M); Email:********@*****.***

CAREER OVERVIEW

CAREER OVERVIEW

CAREER OVERVIEW

Undergoing training on “Advanced ASIC Design and verification” from an institute

“ExpertHDL”, Bangalore. This contains Verilog, System Verilog, Advanced system Verilog, UVM,

Ethernet training, PERL scripting and Synthesis.

SKILLS

SKILLS

VERILOG:

• Expert in writing Verilog Programs.

• Designed UART Control using Verilog.

• Extensive Knowledge of FSM.

• Hands on experience in writing Test Benches.

• Good knowledge of synchronous & asynchronous FIFO.

• Have knowledge of writing Task and Functions.

SYSTEM VERILOG:

• Good knowledge in OOPs.

• Well versed in writing System Verilog Test Benches.

• Performed functional verification of UART controller using System Verilog.

• Performed Code Coverage & Functional Coverage.

• Good knowledge in preparation of Verification Environment.

UVM:

• Good knowledge in writing UVM test benches.

• Verified UART controller using UVM.

• Hands on experience in Stimulus Generation.

PROTOCOLS:

Good understanding of UART, AMBA APB and Basics of Ethernet.

OTHER SKILLS:

Basic knowledge of PER scripting.

PROJECTS AT ExpertHDL

CAREER OVERVIEW PROJECTS AT EXPERT HDL

Project Title: UART Controller.

Description:

UART is a popular method of serial asynchronous communication. Typically, the UART is connected between a

processor and a peripheral. To the processor, the UART appears as an 8 bit read write parallel port that performs

serial to parallel conversions for the processor, and vice versa for the peripheral.

Responsibilities:

Verified in house UART transmitter and receiver through System Verilog Testbench development and

•

generated various test cases to check all operations.

Generated functional and code coverage and worked on coverage improvement by writing various test cases.

•

Project Title: AMBA APB Slave Verification.

Description:

The Advanced Microcontroller Bus Architecture (AMBA) is used as the on chip bus in System On Chip (SoC)

designs.

Responsibilities:

Verified in house APB slave through System Verilog Testbench development and generated various test

•

cases to check all operations.

Generated functional and code coverage and worked on coverage improvement by writing various test cases.

•

ACADEMIC PROJECT

ACADAMIC PROJECTCS

Project Title: MICROCONTROLLER BASED WIRELESS AGROBOT.

Description: The main purpose of this project is to design an embedded based wireless AGROBOT to monitor and

control the soil moisture so as to increase the yield of crop; also the system has to detect and pick the ripped fruits

from the plant.

Project Title: WIRELESS AUTOMIZATION OF WATER MANAGEMENT.

Description: The aim of this project is to design and develop an electronic system that can be employed to

conserve, utilized and manage the water distribution automatically by itself eliminating the man power.

PROFESSIONAL SUMMARY

Fluent in System Verilog, UVM and familiar with System Verilog Assertions.

Well built knowledge of test methodologies UVM and UVM RAL concepts.

•

Languages known: System Verilog, Verilog.

•

Methodologies known : UVM.

•

Tools used: Questasim, Modelsim.

•

SCHOLASTICS

Completed B.E. (ELECTRONICS INSTRUMENTATION) from Basaveshwar Engineering College,

•

Bagalkot. (Visvesvaraya Technological University) in July 2012. Secured 68%

Diploma (ELECTRONICS AND COMMUNICATIONS) from Maratha Mandal Polytechnic, Belgaum.

•

(Department of Technical Education) Secured 65%.

SSLC from Mahatma Gandhi High School (Karnataka State Education Examination Board) Secured

•

70.24%.

STRENGTHS

STRENGTH

• Proficient in grasping new technical concepts quickly and utilizing them in a productive manner.

• Good communicator, problem solving skills.

• Possess ability to work independently or in a team environment within the organization.

• Ready to share knowledge, hard worker.

• Lead the team in the academic project work.

• Practical Thinking about applications.

BEYOND CURRICULUM

BEYOND CURRICULUM

Secured first place in Chess conducted by Electronics & Instrumentation Department.

•

Secured second place in Group Discussion conducted by Electronics & Instrumentation Department.

•

PERSONAL PROFILE

PERSONAL PROFILE

Languages Known : English, Kannada, Hindi, Marathi and Urdu.

Present Address : D/NO 45, 2nd Floor, 4th ‘A’ Cross, 22nd Main, Vinayaka Nagar,

JP Nagar, 5th Phase, Bangalore 78.

Contact this candidate