Power Design
Resume:
OBJECTIVE
MAHENDRANATH. B
To build a long-term promising career with a good firm, which
Mobile: encourages professional growth through a wide range of
994-***-****,09505959 challenging assignments, which would use my skills and Knowledge
536 to gain expertise & enhance my skills.
E-Mail: EXPERIENCE
Mahendra448@gmail.c Worked as a DFT Trainee from January 16-2014 to April 21-2014 at
om
iMSpired solutions Pvt.Ltd.
Address for
Correspondence: SYNOPSIS
S/O B.musalaiah M.Tech (VLSI) studied with good communication skills & able to
H.no:4/148, work in team.
BC colony,
Tarlupadu(po)(md),
Prakasam(dt), ACADEMIC RECORD
PIN-523332. M.Tech 81.21% 2011-2013 Vignan
university,vadlamudi,guntur(dt),
(VLSI) Andhra
Permanent Address: Pradesh.
S/O B.musalaiah
H.no:4/148, B.Tech 73.76% 2006-2010 Prakasam engineering
BC colony, college,
Tarlupadu(po)(md), (ECE)
Prakasam(dt), Kandukur, affiliated by J.N.T.U_K.
PIN-523332.
XII STD 89.6% 2004-2006 Srinivasa padmavathi
Personal Data gautham junior
College, Guntur.
Date of Bord of Intermediate education.
Birth :
07/07/1989 X STD 66.8% 2003-2004 Loyola High
Sex school,markapuram,
: Male Board Of Secondary Education.
Nationality : TECHNICAL RECORD
Indian Tools :
Cadence, Mat lab, xilinx.
Marital Status: Programming Languages : C language, Core java,
Single VHDL, Verilog
Core Subjects : Edc, CS,
Digital electronics, Vlsi, Aicd.
Languages Known :
COMPETENCIES
Telugu, English, Good team player.
Hindi
Organized and well structured at work.
Independent, Self-esteem and self-motivated.
Interests and
Hobbies: Committed to deadlines and schedules.
Music,playing games
I am a member of ISTE.
Preferences
Location: No
constraint
Continued...
AREAS OF INTEREST
> Vlsi Physical Design
> Layout Design
> ASIC System verification
> DFT
> ASIC verification
ACADEMIC PROJECTS
Title: PERFORMANCE ANALYSIS OF A NEW CMOS OUTPUT BUFFER
ABSTRACT:
A new CMOS output buffer with low switching noise and load adaptability is
presented in this paper. The proposed circuit consists of two stages; first
stage is set to reduce switching noise, static power dissipation and also
output ringing. The second stage involves enough speed and full dynamic
range. The performance of the proposed circuit is examined using Cadence
and the model parameters of a 180 nm CMOS process. The simulation results
have confirmed that the proposed output buffer can reduce propagation delay
compared with the previous designs. The topology reports low sensitivities
and has features suitable for VLSI implementation.
Title: ANALYSIS OF TWO NEW VOLTAGE LEVEL CONVERTERS UNDER
VARIOUS LOAD CONDITIONS
ABSTRACT:
Application of level converter in dual supply voltage circuits is one of
the most effective ways to reduce power consumption. To prevent static
current, level converter is introduced as an interface at each low-to-high
boundary. The design of an efficient level converter with least power
consumption and overheads delay is one of the major design constraints. In
this paper, two new level converter circuits with low power consumption are
proposed for less propagation delay and load adaptability. The proposed
level converter circuits are examined using cadence and the design
parameters of a 180 nm CMOS process. The simulation results exhibit that
proposed level converters can reduce propagation delay and increase speed
over the existing circuits available. These level converters are simulated
for different loads and operating conditions. The proposed level converters
can operate at different values of VDDL as +1 V, +1.8 V, +2 V and VDDH of
+3.3 V. Layouts for two new level converters are designed using cadence
virtuso 180 nm technology. The topology reports low sensitivity and has
features suitable for VLSI implementation. The proposed circuits are suited
for low power design without degrading performance.
Title: AN OUTPUT BUFFER FOR 3.3V APPLICATIONS IN A 180 nm +1.8V CMOS
TECHNOLOGY
ABSTRACT:
A new output buffer realized with low-voltage (1.8-V) devices to drive high
voltage signals for 3.3-V interface, such as PCI-X applications in a 180 nm
CMOS process is proposed in this paper. Because PCI-X is a 3.3-V interface,
the high voltage gate-oxide stress is a serious problem to design PCI-X I/O
circuits in a 180 nm CMOS process. The performance of the proposed output
buffer is examined using cadence and the model parameters of a 180 nm CMOS
process. The experimental results have confirmed that the proposed output
buffer can be successfully operated at 100 MHz frequency without suffering
high voltage gate-oxide overstress in the 3.3-V interface. A new level
converter realized with 1.8-V devices that can convert 0/1-V voltage swing
to 0/3.3-V voltage swing is also presented in this paper. The experimental
results have confirmed that the proposed level converter can be operated
correctly without any voltage drop. The topology reports low sensitivity
and has features suitable for VLSI implementation. The proposed circuits
are suited for low power design without degrading performance.
ACHIVEMENTS
* LIST OF PUBLICATIONS/COMMUNICATIONS RELATED TO PROJECT WORK
1. Mahendranath. B and Avireni Srinivasulu, "Performance analysis of a
new CMOS output buffer", in proceedings of the IEEE International
Conference on Circuit, Power and Computing Technologies (IEEE ICCPCT-
2013), Kumaracoil, India, Mar 21-22, 2013, pp. 752-755. ISBN: 978-1-
4673-4920-8. DOI: 10.1109/ICCPCT.2013.6529041.
2. Mahendranath B and Avireni Srinivasulu, "Analysis of two new level
converters with various load conditions," International Journal of
Advances in Telecommunications, Electrotechnics, Signals and Systems
(IJATES2), Vol. 2 No. 3 (2013), pp. 92-98. ISSN: 1805-5443.
3. Mahendranath B and Avireni Srinivasulu, "An output buffer for 3.3V
applications in a 180 nm +1.8V CMOS technology," Accepted for
publication in International Journal of Technology (IJTech), 2013.
ISSN: 2086-9614.
Declaration
I hereby declare that the above particulars are true to
the best of my knowledge and belief.
Place :
Date :
(MAHENDRANATH. B)
CURRICULUM VITAE
Contact this candidate