Engineering Design
Resume:
Elayaraja.R
Kanganipatti,
Muthampatti (Po),
Omalur.(T.k),
Salem (Dt)-636 503. Mobile : +91-
E-mail : ***.******@*****.***
OBJECTIVE:
To apply and expand my engineering skills in the field of VLSI
design, with the opportunity to work on project from conception to
completion.
ACADAMIC CERDENTIALS:
V ME, VLSI DESIGN at Sri Shakthi Institute of Engineering and
Technology, Coimbatore with an aggregate of 70% (until 3rd semester)
V B.E [Electronics & Communication Engineering] from Park College of
Engineering and Technology (Anna University, Coimbatore) in 2011 with
an aggregate of 76%.
V HSC, Sri Jothi HSS School in 2007 with 83 %.
V SSLC, P.K.M HSS School in 2005 with 82 %.
EDA TOOLS:
V Cadence (Virtuoso Schematic, ADE (L, XL) SOC Encounter, rc Launch,
Spectre-S).
V PADS PCB design.
HDL SIMULATOR: Model sim 6.3f, Xilinx ISE 14.4 Suite, Orcad Capture 9.2.
MODULE: Digital Design, CMOS fundamentals, ASIC design flow, Verilog HDL,
RTL Coding.
DEVELOPMENT PLATFORM:
V FPGA (Xilinx Spartan-3E).
V Xilinx ISE 14.4 Design Suite ( Core generator, Timing Enclosure).
V Xilinx Plane Ahead 14.4 (I/O pin Planning Pre -Synthesis & Post-
Synthesis).
PROTOCOLS:
V CAN, knowledge on Ethernet.
TECHNICAL SKILLS:
V Basic knowledge on Analog design(AC and DC analysis of Fully
Differential op-Amplifier)
V Working knowledge on the entire PD flow from Netlist to GDS-II files
(Floor planning, placement & optimization, CTS, Nano Routing, ECO
steps, Timing).
V Good knowledge on Xtalk, EM/IR drops, antenna, DRC and LVS, Formal
verification.
V Basic knowledge on Perl.
TRAINGS:
V Training on ASIC back end flow including practical session. Completed
two test designs starting from Netlist to GDS-II file.
V Trained on Cadence Tools by Cadence Team.
V Effectively completed two blocks from Netlist to GDS-II file.
Block : NCO
Technology : TSMC 180nm.
Clock frequency : 100MHz.
Tools used : SOC Encounter.
PROFESSIONAL EXPERIENCE:
V ATRITY INFO SOLUTIONS (6th Months) - From August 2011 to
January 2012 (Providing solutions for Electronic Board design &
Software)
PROJECT :
V Topics : VLSI IMPLEMENTATION OF SHORT CAN FOR BIT STUFF
REDUCTION
V HDL : Verilog HDL.
V EDA Tools : Xilinx ISE 14.4 Suite -Verification platform.
V Analyzer : Chip scope - Pro.
EXCELLENCY:
V Attended one day workshop on "PCB DESIGN" conducted by NIELIT,
Calicut.
V Undergone In-plant training for two days at "VASANTHA ADVANCED SYSTEM"
in Coimbatore.
PERSONAL PROFILE:
Father's Name : Mr. P. Rajappan.
Date of Birth : 12/03/1990.
Sex : Male.
Nationality : Indian.
Linguistic proficiency : Read, Write & Speak : Tamil,
English.
DECLARATION:
I hereby declare that the information and facts stated above
are true and correct to the best of my knowledge and belief.
Date: Yours faithfully
Place: Coimbatore, India [Elayaraja.R]
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