Engineer Design

Thomas Mathew

Phone:+** - 903-***-**** Email: *******.***@*****.***

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Summary

Energetic and result oriented professional with 2 + years of experience in

the VLSI industry with strong expertise in RTL coding(Verilog),Digital

Design,Custom Design (Digital and Analog),EDA Tool Development and Design

Automation(PERL)

Technical Skills

Proficient in VERILOG HDL, PERL

Scripting,SPICE programming

Programming Languages Working Knowledge of System

Verilog,C,C++

Conversant in Python,Skill

Proficient in Virtuoso Schematic

Editor(ADE-L),Layout Editor (Layout

Tools -XL),Spectre Assura

Basic Working Knowledge of VCS

,ModelSim

Conversant in MATLAB,MAGIC

Verilog Programming,System Verilog

Assertions

Good in Device Physics,CMOS

fundamentals

Strong Expertise in CMOS circuit

/schematic design and Standard Cell

Layouts

Good Knowledge of Network Theorems

Hands on experience in implementing

Core Strengths Schematics and Layouts in Cadence

Virtuoso

Sound Knowledge in Full Custom flow

and Semi Custom flow

Very Strong in Digital Fundamentals

Design Automation and EDA Tool

Development using

PERL (Proficient)

Python,Skill,C(Basic)

ASIC Flow and RTL Design

Very Strong Expertise in PERL

programming

Sound Familiarity with C, Data

Structures and Algorithms,Complexity

Analysis

Good Knowledge of System Memory

Concepts

Got good exposure to Clearcase(Data

Management System)

Professional Experience

Design Engineer at Infineon Technologies Pvt Ltd

March,2013 - Present

The team ANALOG MIXED SIGNAL DESIGN

About the Team basically takes care of IP

integration into either top level

Digital design or Analog design

Developed several PERL scripts for

various applications for the Design

Flow and Methodology for Analog

Mixed Signal Automation Team

Roles and Responsibilities Supported and maintained the

subflows Macroprep (which is

responsible of generating tool

specific views),Ocapi( which

contains the parsers and checks)

based on the customer feedback

Developed various Task Modules for

the new tool IPGateWay which is a

wrapper for Macroprep and Ocapi

which improves the management of

the processes and also provides

improved interface

Full Custom Design- Have Designed

and Implemented(Schematics and

Layout) all Basic Gates,D-FF and

counter in Virtuoso.Simulated in

Spectre.Checked for DRC,LVS and ERC

errors using Assura

Got Basic working knowledge in SKILL

and PYTHON programming

Post Graduate Technical Intern at Intel Technology Pvt Ltd

July,2011 - September,2012

The team GRAPHICS DESIGN AND

About the Team VALIDATION TEAM is involved in the

Design and Validation of various

units in the 3D Graphics Processing

Pipeline. I was involved in

implementing assertions in the 3D

Graphics Pipeline and validating the

media pipeline units

Quality Enhancement of the unit

interfaces in the 3D Graphics

Roles and Responsibilities Pipeline: The basic idea of the

project is to incorporate System

Verilog Assertions and Structures in

the various units and unit

interfaces so that even the corner

cases can be identified and thus

improve the quality of the

interfaces

Development of System Verilog

Assertions - System Verilog

Assertions was developed to assert

various properties which the various

units and unit interfaces should

follow

Automated System Verilog Assertion

Generation

Developed a script using PERL which

Roles and Responsibilities(contd.) takes an excel sheet for a

particular unit as input. The excel

sheet contains various columns for

clock, reset, various components

such as trigger, recur triggers,

delayed trigger, before_event,

one_of etc

Implementation of System Verilog

Structures in the 3D pipeline

Implemented structures in System

Verilog and analyzed the

functionality of the System Verilog

Assertion

Carried out tests for each unit and

worked with validation team to carry

out regression tests

Syntax Checker Tool for Interface

Definition

Roles and Responsibilities(contd.) developed a script which will check

whether all those interface files

follows the same syntax as set by

the designer

Connectivity Checker Tool

to check the connectivity of signals

and also to extract the files

containing the required signals by

parsing and gave support to the

validation team

Comparator Tool

to automate the comparison of data

between the checker files for the

validation team

Provided Support for the Functional

Verification Team

Supported the Verification team by

Modifying the Testbenches as per the

specification changes and verifying

it using the simulations

Running Regression and reporting

Learning the entire signal flow for

2 critical units in the pipeline

and educating the new joinees and

also the parallel teams and was also

involved in various first level

debugs

Technologies Used : System Verilog,

Assertions, Perl Scripting

Tools Used : VCS

Software Engineer in Alamy Images Pvt Ltd

About the Web Development Team - Involved in

Team web Application Development

Involved in Various Internal Web

Roles and Responsibilities Applications

Technologies used : C, ASP.NET using

C#, SQL (for database

manipulations)

Tasks Implemented(Academic)

Project : Ethernet Packet Generator

Tools and Language used : VCS, MODELSIM, VERILOG

Description : In this project we implemented

the Ethernet packet generator as per the IEEE 802.3 format. CRC generation

is done on the Ethernet packet generated.

Designed all Combinational Circuits and many Sequential Circuits such as

Flip Flops in VERILOG

Designed various Analog Circuits in NG SPICE such as Current Mirrors,

Amplifiers,References ..etc

Implemented Layouts for circuits like D- Latch, D - Flip Flop, CMOS

Inverters in MAGIC

Implemented IIR and FIR filter response in MATLAB

Educational Qualification

MS - VLSI CAD Manipal University 8.7/10 (GPA) 2010 -2012

Personal Achievements

Got Instant Recognition Award for the work done in INTEL

Got 91 percentile in GATE 2010

Got A grade in Java programming from the Software Training and Development

Centre of the ER&DCI(C-DAC)

Got 95 percentile in National Aptitude Test conducted by NIIT

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