Engineering Project

AWADHESH KUMAR SINGH (*****EC***)

***EC***

Dept. of Electronics Engineering, IIT-BHU Varanasi

BHU

Room No-89, Dhanrajgiri Hostel

+91-988******* ********.*****.*****@******.**.**

****.*****.*****@******.**.**

IIT-BHU, Varanasi,

Education

Year Degree/certificate University/board Performance

7.52/10

M.Tech (Microwave Engineering) IIT-BHU, Varanasi

Expected 2014

(absolute)

67.64%

B.Tech (Electronics & Communication Engineering) MMM Engineering College, Gorakhpur, U.P

2012 Electronics

64.00%

U.P Board

Class XII

2005

65.83%

U.P Board

Class X

2003

Scholastic Achievements

All India Rank 941 (Top 0.5%) in GATE 2012 amongst 176944 Students.

%)

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All India Rank 426 in JEST 2012 (Organized by IISc Banglore).

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Won 2nd prize in techSHILP in VHDL at techSRIJAN 2010, MMMEC, Gorakhpur.

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Won 2nd Prize in Wireless Robotics at techSRIJAN 2008, MMMEC, Gorakhpur.

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HRD Scholarship : For Teaching Assistantship in IIT-BHU Varanasi for consecutive 3 semesters

Assistantship

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Projects

Title : MODIFIED RHOMBOIDAL DUALBAND ANTENNA FOR BLUETOOTH AND

MODIFIED

UWB APPLICATIONS

Organisation

Organisation: IIT – BHU, Varanasi

M.Tech

Synopsis: In this project, a novel compact, wideband modified rhomboidal dualband antenna

(Under Progress)

with arc shape ground plane that provides dualband operation over the Bluetooth (2.36 -2.49GHz)

and

and UWB ranges (3.1 – 17 GHz) using HFSS software.

Title : LOW POWER 10T SRAM CELL WITH IMPROVED RESPONSE

Organisation: Madan Mohan Malaviya Engineering College, Gorakhpur

Synopsis: This project has emphasized on low power dissipation, read/write delay and stability of

This

B.Tech

SRAM cell and shows the performance of a new 10T cell is compared with traditional 6T cell on

MICROWIND 3.1 simulator.

Mini Projects

Title: TRAFFIC LIGHT CONTROLLER

B.Tech Organisation

Organisation: Madan Mohan Malaviya Engineering College, Gorakhpur

Synopsis: In this project, design and simulate the traffic light controller by using VHDL pro-

In

gramming.

Title : 8 BIT ARITHMETIC AND LOGICAL UNIT

BIT

Organisation

Organisation: Madan Mohan Malaviya Engineering College, Gorakhpur

Engineering

B.Tech Synopsis: The project dealt with implementing the functionality of 8 bit ALU which performs

The

arithmetical, logical and shift operations.

Courses Taken

1. Analog Electronics 6. Analog Communication

2. Digital Electronics 7. Solid State Devices & Circuit

3. Network Analysis 8. VLSI Design

4. Signal & System 9. Analog Integrated Circuits

5. Electromagnetics Theory 10. O-Type Tubes

Skills

Programming Language : VHDL

Simulation Tools : Ansoft HFSS, MODEL SIM, Xilinx, Microwind

Miscellaneous : Microsoft Office, Microsoft Visio

Publications

Awadhesh Singh, Sachin Kalraiya, Gaurav Pandey and M.K.Meshram “Design of Modified Rhomboidal Dualband

•

Antenna for Bluetooth and UWB Applications”, presented at IEEE Students' Technology Symposium 2014 (IIT-

Kharagpur).

Awadhesh Singh, Sachin Kalraiya, Gaurav Pandey and M.K.Meshram “Design of Compact Modified Rhomboidal

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UWB Antenna”, presented at the 2013 International Conference on Microwaves, Antenna Propagation, Remote Sens-

ing (ICMARS-2013).

Sachin Kalraiya, Awadhesh Singh, Gaurav Pandey and M.K.Meshram “CPW-Fed Fork Shaped Slotted Antenna with

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Dual-Band Notch Characteristics”, presented at the 2013 International Conference on Microwaves, Antenna Propaga-

tion, Remote Sensing (ICMARS-2013).

Trainings Attended

Training in VHDL from CetpaInfotechLtd., Noida from July 2010 to August 2010.

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Industrial summer training from NORTH EASTERN RAILWAY.

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Extra Curricular Activities

Member of the winning team in the Hardball cricket tournament 2009.

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Hosted Abhivyakti ‘10 which is the cultural fest of MMM Engineering. College.

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Other Interests

Playing Computer Games, Cricket, Singing.

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