Design Engineer

Name: MADHINENI VAMSI KRISHNA

Email: ************.****@*****.***

Mobile no.: +91-973*******

EmpCode: 1ADADB224038 (RV-VLSI DESIGN CENTER)

Career Objective:

To be an integral part of a dynamic organization where my knowledge and technical skills in

ASIC front-end Design and Verification can contribute to mutual growth and provide

opportunity to work with emerging technologies.

Core Competency:

Good understanding of Verification using System Verilog

•

Extracting Features of Design from a set of Design Specifications and writing a

•

Verification Plan

Developing Self-Checking test bench architecture using System Verilog

•

Writing Constraint Random and Directed test cases using System Verilog

•

Coverage Driven Verification (Functional Coverage and Code Coverage ) using

•

System Verilog

Practical understanding of importance of Interfaces, Mailboxes, Semaphores and

•

Virtual Interfaces in System Verilog

Good knowledge of OOPS concepts such as Polymorphism, Inheritance, Data

•

encapsulation and Class Constructor

Exposure to Verification Environment using SV-UVM

•

Possess skill to understand existing UVM environment and write test cases and

•

sequences

Possess good knowledge of SPI, I2C, UART, AHB protocols

•

Good knowledge of Verilog RTL coding,basic C programming

•

Good knowledge of Synthesis and Static Timing Analysis concepts

•

Good knowledge of Digital Design Concepts

•

Familiar with PERL Scripting language

•

Implemented an FPGA project (Vending Machine using Xilinx) during my

•

undergraduate study

Familiar with Operational Amplifier concepts

•

Possess good communication & interpersonal skills

•

Ability to work both independently and in a team environment

•

Education :

Institute

Degree Discipline Year of Passing Aggregate

University

RV-VLSI Design

PG Diploma VLSI 2014 Completed

Center

Electronics & Vignan University,

BE/B.Tech 2013 73

Communication Guntur

Sri Chaitanya

12th Junior College, 2009 92.6

M.P.C

Hyderabad

Bhashya Public

10th S.S.C 2007 90.5

School, Guntur

Academic Projects:

Title: RTL Design of FIFO using Verilog

Role: Developed Code for RTL design of FIFO

Organization: RV VLSI Design Centre

Description: To design the write, read and reset functionality of

asynchronous FIFO

Tools Used : Questasim

Deliverable/Challenges Faced: Update of read and write pointer after every read / write

operation

Title: RTL Design of UART core using Verilog

Role: Developed Code for RTL design of UART

Organization: RV VLSI Design Centre

Description: To design the transmit and receive functionality of the

UART core

Tools Used : Questasim

Deliverable/Challenges Faced: To come up with the design for the various blocks in

UART such as transmitter, receiver and baud rate

generator

Title: Functional Verification of FIFO using SystemVerilog

Role: Developed Code for Testbench

Organization: RV VLSI Design Centre

Description: To verify the working of FIFO using System Verilog

Tools Used : Questasim

Deliverable/Challenges Faced: Data integrity between Driver and Monitor

Projects going to be completed within 2 months:

Title: Functional Verification of FIFO using UVM

Role: Writing Sequences and Test Cases

Organization: RV VLSI Design Center

To come up with sequences and test cases for FIFO using

Description:

UVM Testbench Architecture

Tools Used: Questasim

Deliverable/Challenges Faced:

Functional Verification of UART, AHB, I2C and SPI

Title:

using UVM

Role: Writing Sequences and Test Cases

Organization: RV VLSI Design Centre

Description: To come up with sequences and test cases for the

protocols using UVM Testbench architecture

Tools Used : Questasim

Deliverable/Challenges Faced:

B.Tech. Project:

Design and Implementation of Automatic Beverages

Title:

Vending Machine

Role: Developed Code for Design

Organization: Vignan University, Guntur

Description: To come up with the VHDL implementation of an

FPGA-based vending machine based on Mealy model

Tools Used : Xilinx-ISE and Cadence

Achievements:

Finalists in Vignan-Voice cricket competition

•

Secured school first in class 10, 2007

•

Captained my school cricket team

•

Personal Profile:

Name : Madhineni Vamsi Krishna

: 11th June 1992

Date of Birth

: D-no: 15-122-1, State Bank Colony, Dharmavaram, Guntur(Dist),

Address

Andhra Pradesh-515671

Father Name : M. Subramanyam

Nationality : Indian

Sex : Male

Languages known : English,Telugu

Contact this candidate