Familiar in writing fully automated test benches in system Verilog,UVM

RESUME

Srujana Yatham H.No:**, G-Floor, Nivrita Nilaya, 2nd

Sector,

HSR Layout, Bangalore-560192,

Landmark: Next to Power Station.

Mobile: +91-994*******,

*******.******@*****.***.

Objective: Seeking a challenging position in VLSI design and/or

verification where my skills and experience will enhance the company's

success and put forward my personal growth while being innovative,

optimistic and resourceful.

Professional Experience:

. Three years of experience as Verification Engineer in Team Embedded

Technology, Hyderabad.

Education:

. M.Tech in VLSI System design from JNTUH with distinction [71%] (Oct

2008 - Jan 2011).

. B.Tech in Electronics and Communications Engineering from JNTU,

Hyderabad with first class [63%] (June 2004- May 2008).

. Intermediate from Intermediate board of Andhra Pradesh with

distinction [84.4%] (June 2002-April 2004).

. SSC from Secondary school of education, Andhra Pradesh with

distinction [77.8%] (April-2002)

Skills:

. Hardware Languages: Verilog & System Verilog

. Familiar in developing appropriate test vectors using System Verilog

language.

. Familiar in writing fully automated test benches with random

verification.

. Familiar with functional verification in test environment.

. Familiar in APB/AHB/AXI protocol understanding

. Familiar in Code coverage analysis

. Functional coverage driven verification

. Familiar in Behavioral model & Test bench development

. ASIC Methodologies: UVM, RTL and Behavioral

. Operating Systems: UNIX, Windows

. Exposure to Tools: Xilinx, Model-Sim

Projects:

Project 3:

AHB-APB Bridge Design & Verification

Role: Verified the functionality AHB-APB Bridge in UVM Methodology.

Key Features & Description: AMBA AHB is a new level of bus which sits above

the APB and implements the features required for high-performance, high

clock frequency systems including burst transfers, split transactions,

single cycle bus master handover, single clock edge operation, non-tristate

implementation, wider data bus configurations (64/128 bits).

The AMBA APB should be used to interface to any peripherals which are

low bandwidth and do not require the high performance of a pipelined bus

interface. APB peripherals can be Integrated easily into any design flow,

performance is improved at high-frequency operation, Performance is

independent of the mark-space ratio of the clock, static timing analysis is

simplified by the use of a single clock edge, no special considerations are

required for automatic test insertion, and Application-Specific Integrated

Circuit (ASIC) libraries have a better, selection of rising edge registers.

Project 2:

SPI Master Core Specification

Role: Verified the functionality and Code Coverage of SPI Master Core

Specification in UVM Methodology.

Key Features & Description:

. Full duplex synchronous serial data transfer

. Variable length of transfer word up to 128 bits

. MSB or LSB first data transfer to 1 or 8 slave select lines

. Receive and Transmit on both rising or falling edge of serial clock

independently

. Fully static synchronous design with one clock domain

. Fully synthesizable

Project 1:

ROUTER 1X3 Design and Verification

Role: Designed & verified with Code Coverage of Router1X3 using Verilog and

UVM Methodology.

Description: Router is a device that forwards data packets between computer

networks. It is an OSI layer 3 routing device. It drives an incoming packet

to an output channel based on the address field contained in the Packet

header.

Key Features:

Packet routing: The packet is driven from the input port and is routed to

any one output port, based on the address of the destination network.

Parity Checking: An error detection technique that tests the integrity of

the digital data being transmitted between server & Client. This technique

ensures that the data transmitted by the server network is received by the

Client network without getting corrupted.

Reset: It is an active low asynchronous input that resets the router. Under

rest condition, the Router FIFO's are made empty and the valid out signals

goes low indicating that no valid packet is detected on the output data

bus.

Curriculum Project (M.Tech):

MULTI CHANNEL UART CONTROLLER BASED ON FIFO AND FPGA

Description: To meet modern complex control systems, communication demands

a Multi-channel UART based on FIFO technique and FPGA. It deals with design

method of Asynchronous FIFO circuit and UART circuit in FPGA. The Multi-

channel UART controller can be used to implement communications when master

and slave equipments are set at different baud rates. It can be used to

reduce synchronization errors between sub-systems in a system with several

sub-systems. This architecture used for efficient data transmission with

multiple baud-rates and to increase the data bus utilization. This

architecture reduces the time delay between sub-controllers and also it

reduces synchronization errors. The channels of Multi-Channel UART (MUART)

are designed to reduce the CPU overhead when working with high speed modems

and other devices. The Multi-Channel UART Controller operates in three

modes namely Normal mode, Hub mode and Bridge mode.

Academic Project (B.Tech):

Wireless Mobile Bomb Disposal Unit

Environment : Embedded Systems

Description: An effective Bomb Disposal Unit (BDU) can reduce or eliminate

the risk of potentially deadly scenarios and allow a bomb technician to

focus on disabling the device. The same feature can be extended to be used

in the war fields where the army might be required to go into the hostile

situations where mines could have been laid. In such situations in case the

human beings are allowed to go traverse over them there will be a major

loss in the human resources. Thus a need arises to diffuse or locate a mine

from a distance. Even if a BDU cannot diffuse a device, it can still relay

information to aid in selecting tools and procedures before a technician

approaches a device. We designed a robust wireless mobile bomb disposal

unit that would be capable of reaching close to the objects of threat and

real scenario can be observed through an onboard video camera which can

send back video feedback to the observatory.

Key Strengths:

. Time Conscious

. Flexible enough to pick up new skills, idea and stimulate personal

and professional growth

. A good team player and positive Attitude

Extra Curricular Activities:

. Participated in National Level Technical Sympoism (Paper Presentation

on VLSI) at Narayana Engg College, Nellore.

. Active Participation in Singing, Drawing and Painting contests.

Personal Details:

. Date of Birth: 13-07-1987

. Language Known: English, Telugu and Hindi

. Nationality: Indian

. Marital Status: Married

I declare that the details given above are true to the best of my knowledge

and belief.

Srujana Yatham

Date:

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