Project Design

ANOOR DHARANI.V ***-A Kurinji Nagar,

*************@*****.*** P.K Road,

+91-944******* Kangayam - 638 701

OBJECTIVE

Seeking a rival position under the domain where I can contribute my skills for organization’s

success and synchronize with new technology.

ACADEMIC CHRONICLE

INSTITUTION/ YEAR OF

COURSE BOARD/UNIVERSITY PERCENTAGE

COLLEGE PASSING

BE (Electronics and Tamilnadu

Anna University of 2014

Communication College of 8.477 (CGPA)

Technology, Chennai

Engineering) Engineering

E.H.K.N Matric

HSC Matriculation 2010 92.3

Hr. Sec School

Jaycees Matric

SSLC Matriculation 2008 92

Hr. Sec School

SKILL SET

EDA Tools : Tanner Tools (S-Edit, T-Spice and W-Edit) and Xilinx 9.2

Software Skill : Basics of C.

AREA OF INTEREST

Digital Electronics (Gate, Flip Flop and Counter)

VLSI Design (CMOS)

PROJECT WORK

: “DESIGN OF PFD-CP MODULE FOR A PLL”

Title

Description: In this project, simulation and comparative analysis of various designs of Phase Frequency

Detector (PFD) and Charge Pump (CP) has been performed and introduced three novel approaches to

reduce the dead zone in PFD and a modified design of CP to minimize the current mismatch. The overall

module for Phase Locked Loop (PLL) consists of modified design of PFD with dead zone of about 0.3ns

and improved CP with the current mismatch of about 0.1uA

ACHIEVEMENTS

Project Expo

I have exhibited and demonstrated the project titled “CELLPHONE DETECTOR” in the

“PROJECT EXPO 2012” held on 24th February 2012 and won III prize.

I have exhibited and demonstrated the project titled “ANTI-BAG SNATCHING

DETECTOR” in the “PROJECT EXPO 2013” held on 11th April 2013.

In-Plant Training

Undergone Fundamentals of Telecom Training at BHARAT SANCHAR NIGAM

LTD. Erode.

Conference

Presented a paper titled “Design Of Various PFD And Charge-Pump Architectures For A

PLL –A Survey” in the National Conference on “Emerging Trends In Data Mining

(ETIDM)” held on 3rd and 4th September 2013.

Presented a paper titled “Comparison and Analysis of Various PFD Architecture for a

Phase Locked Loop Design” in “2013 IEEE International Conference on

Computational Intelligence and Computing Research (ICCIC)” held from December

26 to December 28, 2013.

Journal

My paper titled “Design of Various PFD and Charge-Pump Architectures for a PLL –A

Survey” has been published in the “CIIT INTERNATIONAL JOURNAL” on 2013.

My paper titled “Comparison and Analysis of Various PFD Architecture for a Phase

Locked Loop Design” has been published in IEEE XPLORE on 2014.

Academics

I have got “EXCELLENCE IN ACADEMICS” prize for the academic year 2013.

I have attended a one day workshop on “TANNER EDA & MENTOR GRAPHICS TOOLS”

held on 13th march 2014 at Tamilnadu College of Engineering, Coimbatore.

PERSONAL DETAILS

Father’s Name : Mr. N. VETRIVEL

Mother’s Name : Mrs. V. SIVAGAMI

Date of Birth : 12-02-1993

Gender : Female

Languages Known : Tamil, English

Nationality : Indian

DECLARATION

I hereby declare that the particulars given above are true to the best of my knowledge and belief.

Place: Coimbatore

Date: (ANOOR DHARANI.V)

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