Project Engineering
Resume:
Divya. G
***********@*****.***
Career Objective:
Seeking employment opportunities where I can provide talents, cultivated skills set, and an
honest, hardworking personality to positively impact an organization.
Technical Qualification:
B.E in Electronics and Communications Engineering with 8.27 CGPA from Tamilnadu College
of Engineering in Coimbatore in the year of 2014.
Academic Qualification:
HSC with 92.75% from Sri Vidya Mandir Matric MHSS Uthangarai at the year of 2010.
SSLC with 85% from Lions MHSS Tirupattur at the year of 2008.
Software Exposure:
Programming Language : Basic of C, C++
Networking : CCNA
Technical Software : Xilinx 9.2, Tanner Tools (S-Edit, T-Spice, W-Edit and L-Edit)
Documentation software : Microsoft Office, Excel, PowerPoint.
Area of Interest:
Computer Networks
VLSI
Academic Projects:
Phase:1
Title: Modified Phase Frequency Detector for a PLL
In this project simulation and comparative analysis of various designs PFD has been
performed and introduced three novel approaches to reduce the dead zone in phase frequency
detector (PFD) for PLL application.
Phase:2
Title: Design of PFD –CP Module for a PLL
In this project an improved charge pump (CP) is proposed with perfect current
matching characteristics. The modified PFD and improved CP are integrated to from an
overall module for a PLL.
Publications:
Design of various PFD and charge pump architectures for a PLL – survey has been published in
the CIIT International journal on 2013.
Comparison and analysis of various PFD architectures for phase Locked loop has been published
in the IEEE Explore website on 2013.
Awards & Accolades:
Underwent one week in plant training programming in BSNL (Vellore).
Complete course in Diploma in Networking, ICS IT training center Coimbatore.
Won 3rd Prize in project expo held in 2012 in the Tamilnadu college of Engineering.
Presented a paper title “Design of various PFD charge pump Architectures for a PLL – A survey”
at the National conference on Emerging trends in data mining (ETIDM).
Presented a paper titled “Comparison and Analysis of Various PFD Architecture for a Phase
Locked Loop Design” in the 2013 IEEE International Conference on Computational
Intelligence and Computing Research (ICCIC)”held on 26th and 27th December 2013.
Attended one day workshop with Tanner EDA And Mentor Graphics Tools on March 2014.
Interpersonal Skills:
Adapt to changing environment.
Effective communication skills, teamwork and leadership qualities.
Very friendly and willing to accommodate with any situation.
Personal Particulars:
Father’s name : P.Govindaraj
Date of birth : 09.10.1992
Sex : Female
Languages known : English, Tamil
Address : H.I.G No:2 phase II
TNHB Tirupattur
Vellore-635601.
Declaration:
I do hereby declare that all the particulars given herein above are true, correct and complete to the best
of my knowledge and belief.
Date:
Place:
[G. DIVYA]
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