ASIC Design and Verification

Gaurav Jayawant Gawali

Flat #***, Om sai emerald apt, 8th main, 6th cross, vinayak nagar, murgeshpalya, Banglore -560017

Mobile: +91-903******* / +91-812*******

Email: ******.******@*****.***

LinkedIn: in.linkedin.com/pub/gaurav-gawali/25/694/93b/

Objective: To work on challenging tasks and gain expertise in the field of VLSI.

Education

Master of Technology in VLSI Design (2012-2014)

VIT University, Vellore, Tamilnadu (CGPA: 8.36/10)

Bachelor of Engineering in Electronics and Telecommunications (2006-2010)

Pune Institute of Computer Technology, Pune, Maharashtra (Percentage: 61.47 %)

H.S.C. (2006)

K.T.H.M. College, Nashik, Maharashtra (Percentage: 89.83 %)

S.S.C. (2004)

Maratha High school, Nashik, Maharashtra (Percentage: 85.33 %)

Areas of Interest

Digital system Design

Physical Design

SoC Design

FPGA based system Design

ASIC Design and Verification

Tools and Languages

HDL : Verilog HDL

Pre-layout Simulator: Altera ModelSim & Quartus II, MATLAB

Synthesis Tool: RTL Compiler (Cadence)

Post synthesis simulation Tool: NCLaunch (Cadence)

Back end Tool: SoC Encounter (Cadence)

Power Simulation Tool: QuestaSim (Mentor Graphics)

DRC/LVS Tool: Virtuoso (Cadence)

Parasitic Extraction Tool: Assura RCX (Cadence)

Advanced Simulation for Custom IC's Tool: Virtuoso ADE (Cadence)

Programming Skills: Verilog HDL, MATLAB, Basic C

Scripting Languages: Perl, TCL

Technical Skills

Thorough knowledge of ASIC Design(front end) Flow, Physical Design(back end) from RTL to GDSII tapeout.

Familiar with methodologies like chip level timing (STA), floorplanning, place and route, CTS, low power

techniques.

Publications

Journal:

“Implementation of Fixed and Floating Point Square Root using Nonrestoring Algorithm on FPGA”

I.

Contributors: Anuja Nanhe, Gaurav Gawali, Shashank Ahire and K. Sivasankaran

published in International Journal of Computer and Electrical Engineering, Volume 5 Number 5

(Oct. 2013).

"Clock Network Synthesis Based on Dual-MST Algorithm "

II.

Contributors: Shashank Ahire, Anuja Nanhe, Gaurav Gawali and John Reuben

accepted for the journal International Journal of Applied Engineering Research (IJAER) and will be

published very soon.

III. "Implementation of High Data Rate AMBA AHB for On Chip Communication"

Contributors:, Shashank Ahire,, Gaurav Gawali, Anuja Nanhe and K. Sivasankaran

accepted for the journal International Journal of Applied Engineering Research (IJAER) and will be

published very soon.

Conference:

“ Implementation of Fixed and Floating Point Square Root using Nonrestoring Algorithm on FPGA”

Contributors: Anuja Nanhe, Gaurav Gawali, Shashank Ahire and K.Sivasankaran

published in 5th International Conference of Electronics and Computer Technology (ICECT)-June,2013.

Work Experience

Organization: CVC Pvt. Ltd.

Location: Banglore, Karnataka.

Designation: Intern.

Period: October 2013- present

Organization: K.K. Wagh Institute of Engineering Education and Research.

Location: Nashik, Maharashtra.

Designation: Lecturer.

Period: January 2011- May 2011

Projects

Title: Low Power Design and Verification of SPI IP in a system -on-chip context

Company Name: CVC Pvt ltd., Banglore.

Language: Verilog HDL, UPF commands

Tools: Questa Sim

Description: Verification of SPI and APB-SPI is performed using different test-cases in verilog HDL.

Also, The management of power consumption is performed by using Questa's Power A ware simulation along with

unique design of Accellera's Unified Power Format (UPF) standard modeling of low power behavior early in the

design cycle.

Title: Clock Network Synthesis based on Dual-MST Algorithm.

Language: MATLAB

Tools: MATLAB, LTspice

Description: In this project, a symmetric tree is implemented for ISPD2010 benchmark derived from Intel 45nm

designs which provides minimum skew and minimum length of wire.

Accomplishment: Received award for one of the best projects in Science, Engineering and Technology

Conference 2013 held at VIT University, Vellore.

Title: Implementation of High Data Rate AMBA AHB for On Chip Communication

Language: Verilog HDL

Tools: Cadence NCLaunch, SoC Encounter, Cadence RTL Compiler

Description: Project shows significant improvement in terms of clock cycles and operating frequency due to

use of FIFO as a slave. The physical synthesis of the design is performed along with logic synthesis.

Title: Implementation of Fixed and Floating Point Square Root using non restoring Algorithm on FPGA

Language: Verilog HDL

Tools: Altera ModelSim & Quartus II.

Description: In this project, pipelined architecture using non restoring algorithm results in reduced area in

terms of logic elements when compared to restoring algorithm.

Achievement

th

Merit Holder (19 Rank), HSC examination in Nashik Divisional Board, Maharashtra in 2006.

One of the best project holders in Science, Engineering and Technology Conference 2013 held at VIT University,

Vellore.

Personal Details:

Name: Gaurav Jayawant Gawali

Date of Birth: 30/04/1989

Permanent Address: 23"Sushila", sahadev nagar, near Chintamani Lawns, Pumping Stn, Gangapur Road,Nashik -

422013, Maharashtra.

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