Design Power

Wenshuo He

**** ****** ***, *** ****, CA ******@********.*** 347-***-****

EDUCATION

Columbia University, School of Engineering and Applied Science, New York, NY 12/2013

Master of Science in Electrical Engineering, GPA: 3.85 / 4.0

Relevant courses: Formal Verification of HW System, Digital VLSI Circuits, Advanced Logic Design, CAD of

Digital Systems, Advanced Digital Electronic Circuits, Computer Architecture.

Beijing University of Posts and Telecommunications, Beijing, China 07/2012

Bachelor of Science in telecommunication engineering, GPA: 3.5 / 4.0

WORK EXPERIENCE

Columbia University, New York, NY

09/2013 – 12/2013

Teaching Assistant for Advanced Logic Design

PROJECT EXPERIENCE

09/2013 – 12/2013

Formal verification: I2C Slave Controller

Developped a Moore FSM controller specification for a slave device on I2C bus protocol, where the

slave can be either a receiver or transmitter. Described in Verilog.

Executed formal verification of the I2C Slave Controller using Mentor Questa Formal tool.

Wrote assumptions to constrain input sequence and assertions to check property.

02/2013 – 05/2013

ASIC Design: Low Power Amber23 ARM-compatible core

Applied Bubble Razor, a low power technique which provides timing speculation and error correction for

low supply voltage designs, on Amber 23, an open-source 32-bit RISC processor.

Synthesized the design using Design Complier, and retimed it from flip-flop-based to latch-based.

Used PrimeTime to find critical path and replaced the latches on critical path with Bubble Razor latches.

Generated a DRC clean custom layout with the aid of Auto Place and Route.

Compared the power consumption of the original design and low-power design using Ultrasim.

09/2012 – 12/2012

ASIC Design: Trigonometric FP Function Unit

Created the pseudo code for a custom trigonometric FP Function Unit with variable precision.

Drew the General Algorithmic State Machine Diagram, and optimized it in Register Transfer Level.

Built the FP Function Unit by Verilog in Quartus and verified its correctness by simulations.

09/2012 – 12/2012

VLSI Design: An 8-bit Microprocessor Core in 90nm CMOS Technology

Designed an 8-bit core, composed of memory(SRAM), adder, shifter, PLA and tri-state bus controller.

Utilized Cadence to design and simulate the schematics of each component of the microprocessor core.

Completed manual layout on Virtuoso and obtained a DRC and LVS clean verification, then simulated

with layout parasitic extraction to fully prove functionality and analyzed delay, power consumption.

TECHNICAL SKILLS

Computer Language: Verilog, C, VHDL, Perl, System Verilog, JAVA, Python, Matlab

Research Tools: Cadence, Quartus, Matlab, Primetime, Ultrasim, Questa Formal

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