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Email:*************@*****.***
RAVINDRA M. VEGAD
CAREER OBJECTIVE:
Seeking a technical position in the field of VLSI Engineering and helping to achieve organizational goals.
ACADEMIC QUALIFICATION:
COURSE INSTITUTION YEAR OF PASSSING % or CGPA
B-Tech Dr.B.A.T.University, 2012 6.61(CGPA)
Lonere
HSC Thomas Baptista Junior 2008 76.83
College,Maharashtra
SSC Gnan Mandir Vidhyalaya, 2006 84.93
Maharashtra
CORE SKILLS:
• Good Understanding in ASIC Flow (SOC Verification).
• Experience & Good Understanding in Digital design architectures and RTL coding
• Good knowledge of FPGA Design Flow
• Hardware design using Verilog.
• Experience in System Verilog.
• Experience on perl and shell scripting.
• Digital Design, FSM, CMOS Ckt.
• Experience in CADENCE EDA tools like: NCVerilog, NCSim, SimVision, RTL Compiler,SOC Encounter.
• Verifications of system using System Verilog.
AREA of INTEREST:
• Circuit Designing and verification.
• Programming in Verilog, System verilog.
PROJECT & TRAINING:
ASIC VERIFICATION PROJECTS:
MINI PROJECTS:
• Synchronous FIFO Design
• Sequential Multiplier Design
• Traffic Light Controller Design
MAJOR PROJECTS:
APB LITE PROTOCAL:
PROJECT DESCRIPTION:
• Literature Survey to understand APB Protocol
• Prepared Detailed Design Document For APB Implementation
• Verilog Coding and simulation using Cadence NCVERILOG tool.
• Test bench implemented in System Verilog for Verification.
B.TECH ACADEMIC PROJECTS:
Project on Electrocardiogram Data Acquision.
TRAINING:
• Vocational Training at Sangam electronics,Surat.
Post Diploma in VLSI Design at Indian Institute of VLSI Design and Training.
PERSONAL STRENGTHS:
• Leadership and Growth Potential.
• Hard working and Adaptability.
• Willingness to learn & develop.
PERSONAL DETAILS:
Father’s Name : Mohanbhai Vegad
Gender : Male
Nationality : Indian
Marital Status : Single
Languages Known : Gujarati, Hindi, English, Marathi,
Hobbies & Interests : Organizing Events & Activities, Travelling, Making Friends, Reading Novels, Browsing,
Playing chess.
Professional Experience:
Worked at Advanced photonics India as an application engineer from December 2012 to May 2013.
DECLARATION:
I do hereby declare that all the particulars made above are true to the best of my knowledge and belief.
Date :
Place : Bangalore (RAVINDRA M. VEGAD)