Engineering Signal Processing

Vishnu Priya D

Mobile: +919********* Email: ******.*********@*****.***

DOB: 26-Jan-1992

Objective

Seeking a position to utilize my skills and abilities that offers

professional growth while being resourceful, innovative and flexible.

Key Skills

. Consistent good academic record.

. Good analytical and communication skill.

. Hard work

Academics

Course Institution Examination Month & Year Aggregate

of passing Percentage

Authority

B.E Kings College of Anna April 2013 76.2

(ECE) Engineering,Punalkulam, University

Pudukkottai.

H.SC Government Girls Higher TN State March 2009 86

Secondary School, Orathanadu. Board

SSLC Government Girls Higher TN State March 2007 88.4

Secondary School, Orathanadu. Board

Technical Expertise

. Operating System : Windows XP/2007

. Package : Microsoft Office

. Technical : Basics of C,C++, Assembly Language

Area of Interest:

. Embedded System

. Micro Processor

. Digital Electronics

Professional Training

. Undergone In-plant training at Bharat Sanchar Nigam

Limited,Thanjavur

. Participated in the two-day National Level Seminar on "Emerging

Technology in Mixed Signal Processing" at Arasu Engineering

College, Kumbakonam.

Awards and Achievements

. Participated in the "Second National Level Technical Symposium" at

P.A. College of Engineering and Technology, Pollachi.

Projects Profile

FPGA implementation of a Single-input fuzzy logic controller for boost

converter with the absence of an external analog to digital converter

Soft ware : Xilinx

Device : FPGA kit

Project Description: In this paper, the single-input fuzzy logic controller

(FLC) (SIFLC) for boost converter output-voltage regulation is proposed.

The SIFLC utilizes the signed distance method that reduces the

multidimensional rule table. The SIFLC is compared to the proportional-

integral controller. Another feature of this work is the absence of an

external analog-to-digital converter (ADC). Instead, a simple analog-to-

digital conversion scheme is implemented using the FPGA itself

Personal

Sex : Female

Marital Status : Single

Nationality : Indian

Languages Known : English and Tamil

Address : 74,Yanaikkara Street,

Orathanadu (T.K),

Thanjavur(D.T)-614625

Declaration

I hereby declare that the above-mentioned information is correct up to my

knowledge and I bear the responsibility for the correctness of the above

mentioned particulars.

Place: Orathanadu (Vishnu Priya

D)

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