Development Design Engineer

VINAY DHAWAN

Projects Details

Standard Cell Ultra Low Power Library Development in 0.18 um technology.

Responsibilities:

Layout development of Standard Cell library.

Physical verification of Standard Cell library.

STSCL (Sub Threshold Source Coupled Logic) Library Development in 0.18 um

technology.

Responsibilities:

Layout development of STSCL library.

Physical verification of STSCL library.

Worked on the Layout development of SRAM (512x8) in 0.18um technology.

Responsibilities:

Layout development of 128x128 bit core block.

Layout development of control block.

Physical Verification (DRC & LVS)..

Working on the Layout development of SRAM (32x16) in 0.18um technology.

Responsibilities:

Schematic development of top block through netlist.

Layout development .

Physical verification.

Achievements

EVENT CORDINATOR of the college TECHFEST TECHNIKOS'11 held in I.E.T.

Bhaddal.

Winner: 2nd prize at PEC in Boffin Quest(National Level).

1st Prize in Junkyard at I.E.T Bhaddal.

Technical Executive of Technical Club-IET BHADDAL

Declaration

I hereby declare that the above information given by me is true to the best

of my knowledge.

Vinay Dhawan

Contact Address: Objective

Preet Nagar,Gali No.1 To secure a challenging position where I can effectively

Mandi Gobindgarh contribute my technical skills as a professional in the

Distt. Fatehgarh Sahib industry that offers professional growth while being

(Punjab) resourceful, innovative and flexible.

Ph:+91-844*******

E-mail:

*********@*****.*** Profile

10 months of Experience in Standard cell and Memory

Layout.

My Strengths: Physical verification.

Antenna checks.

Innovative Standard Cell Library development.

Self-motivated

Positive approach Educational Qualification

Adaptable to changes B.Tech (Electronics and Communication) with 76% from IET

Team Spirit towards work Bhaddal, Punjab (PTU) in 2012.

Diploma (Electronics and Communication) with 72% from

Mehr Chand Polytechnic College(P.S.B.T.U),Jalandhar.

Personal Data: 10th with 70% from Gobindgarh Public School (C.B.S.E),

Date of Birth : Mandi Gobindgarh in 2005.

9-10-1989

Sex :

Male Employment Details

Nationality : Worked with RF Silicon Pvt. Ltd as a Design Engineer

Indian from 14th January 2013 to till date.

Languages Known : Hindi,

English,Punjabi.

Technical Skills

Permanent Address

Preet Nagar,Gali No.1 Simulation Tools : Cadence Spectre, Synopsys HSIM

Mandi Gobindgarh Design Tools : Cadence Virtuoso, Schematic

Distt. Fatehgarh Sahib Composer,

(Punjab) Spice Pro(from netlist to schematic), gds

Ph:+91-844******* to ASCII converter.

Physical

Verification Tools : Mentor Calibre, Synopsys Hercules

(for LVS and DRC)

Scripting Language: Perl

Operating Systems: Windows platform, Linux

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