Power Plant Design

Arun Poonia Ph:312-***-****

Apt#*R, *** W **st Street Chicago, IL-60616 Email: ***********@*****.***

EDUCATION

Master of Science, Electrical Engineering Jan 2012- Present, GPA: 3.44

Illinois Institute of Technology, Chicago, IL

Course Taken: Introduction to VLSI, Computer Advanced Architecture, Hardware Software Co-design,

High Performance VLSI/IC Systems, Advanced VLSI Design, Microcomputers, Computer vision and image

Processing, CAD Techniques for VLSI Designs, Object Oriented Computer Simulation.

Bachelor Of Engineering, Electronics & Communication Engineering- May 2010

Jai Narain Vyas University, Jodhpur, INDIA

Cumulative Percentage: 70.53%(Honors)

Skills

Programming Languages: Verilog, VHDL, C, C++, Matlab, SystemC, Assembly, TCL, Perl.

Operating Systems: Windows (XP, Vista, 2003, 2008, Win7), UNIX, LINUX.

Tools: Cadence, ModelSim, Eclipse,Virtuoso, Simvision, Synopsys HSPICE, CAD.

Academic Projects

Register Transfer Level Power Reduction

Used Verilog programming to perform RTL power reduction techniques-memory splitting

and operand isolation-on given design. Power and timing analysis of these two methods was

performed using HSPICE and compared with original design.

Design And Synthesis Of Carry Propagation Adder

Used Verilog programming to design various adders-Carry Skip Adder, Carry Select Adder,

Carry Ripple Adder and Kogge Stone adder. Performance, timing, power and area were

evaluated and compared using HSPICE.

Simulation Of CPU, Cache, Bus And Memory Data Path

Used VHDL programming to implement 32 Bit Microprocessor without Interlocked Pipeline

Stages(MIPS) Processer. Various modules within Processor-CPU, Memory, Cache and Bus-

were implemented using Verilog coding. Within Cache operation, Write Through and Write

Back strategies were used.

Carry Ripple Adder Using Data Driven Dynamic Logic

Designed Carry Ripple adder and implemented it using Data Driven Dynamic logic and Split

Path Data Driven Dynamic Logic under 45 nm technology nodes. Schematic design was done

using Cadence IC 6.1 tool and simulated using Synopsys HSPICE. Power and Time analysis

was done using Nanosim and compared with HSPICE results.

Design Of Monitor Program

Used assembly programming to design a monitor program which takes several input

commands. For proper performance of these commands, Command Interpreter, twelve

different debugger command, Exception handlers and help blocks, were written in the

program. Performance evaluation of program and simulation was performed using Easy68 k

simulator.

Fast Fourier Transform On Network-On-Chip Architecture

Used SystemC programming to design a 3X3 2D- mesh Network-On-Chip model and

evaluated the model using Fast Fourier Transform.

Design Of Logic Simulator

Designed a Digital logic simulator to simulate a circuit written in EasyVL language for

understanding the CPU. Visual studio C++ was used for programming purpose. Functions like

Iterations, Template, Constructor, Classes, Containers and Algorithms for creation of Lexical

Analyzer, Syntactic Parser and Simulator modules were also used.

Segmentation Of Sampled Images And Application of Discriminate Methods

Used MATLAB programming to segment the given images using threshold, mean, median

and histogram segmentation methods and performance evaluated.

Work Experience

Illinois Institute of Technology, Chicago, Illinois

Student Assistant, Aug 2012- Present

As a student assistant at my college TV department. My responsibilities are record the lecture with no

error. I make sure that there is no technical difficulty associated with broadcast.

Tata Consultancy Services, Kolkata, India

Assistant System Engineer, Sep 2010- Dec 2011

I worked as a team member of various teams which involved Java, Mainframe, C and C# projects. I was

responsible of testing banking application for CITI Bank. My achievement during my employment was

reduced the testing by 10%.

Nuclear Power Corporation India Limited, Mumbai, Maharashtra, India

Intern, Jun 2009-Aug 2009

Nuclear Power Corporation of India Limited is responsible for design, construction, commissioning and

operation of nuclear power reactors in India.

Implementation of master slave concept on cold fire CPU board using FPGA programming

Cold fire unit controls various operations in the plant. The project objective was to ensure

that redundant CPU assumes master operations in case of cold fire unit failure. Work

included designing, programming and debugging of the circuitry.

Project work was implement in Nuclear Industry and received appreciation from Director.

National Thermal Power Corporation Limited, Rihand, Uttar Pradesh, India

Intern, Jun 2008- July 2008

National Thermal Power Corporation is India’s largest company in generating power sector in every

area. It supplies power to every region of India.

To analyse the power generation process in thermal plant

Studied Max DNA distributed control system and its features in thermal power plant

Underwent training in Control Section for two months and submitted report

Academic Achievements

1st Prize and the Best Team Certificate in Inter-school science competition 2004(Rocket Modelling)

organized by Science & Research Department Rajasthan Government, India -2004

Ranked 9th in the Inter-district Science Quiz conducted by CLC, Sikar, Rajasthan, India -2005

1st Prize among 500 students in the annual PCM quiz, Rajasthan Public School, India -2005

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