M.Tech, Verilog, VHDL, C
Resume:
RESUME
N.RAJASEKHAR
M.Tech (Electronics), Email :
**********.***@*****.***,
Pondicherry University (A Central University), Mobile :
Pondicherry, India. DOB : 14-07-1990.
Career Objective
To work in the challenging environment with an organization that
provides ample opportunities to learn, contribute and to grow.
Academic Profile
Course Institute Board/Universit Year of % of
y passing Marks/CGPA
M.TECH Pondicherr Pondicherry Pursuing(2 8.48
(Electronics) y University 012-2014)
University
B.TECH VITS, JNTU Anantapur 2011 72.97%
(E.C.E) Proddatur
INTERMEDIATE Smt. Board of 2007 93.3%
(M.P.C) Theresa Intermediate
Jr. Education, AP
College
S.S.C Government Board of 2005 87.8%
High Secondary
School education, AP
Courses Under Taken
> ASIC design
> Digital design through Verilog HDL and VHDL
> Low power VLSI design
> MOS Device modeling
> Digital Signal processing and Communication Systems
> Electronic Devices and Circuits
Other Subjects:
Fundamentals of Managerial economics and Financial Analysis,
Management Studies, Computer Networks, C programming and Basic JAVA,
Communication Skills and Soft Skills
Lab Work:
VLSI and Embedded Systems, Xilinx Lab, Digital Circuits, Network
Theory, communication systems, Analog and Digital IC Design, C programming,
Microprocessor and microcontroller Interfacing.
Area of Interest
> Digital design through Verilog HDL and VHDL
> Low power VLSI design
> MOS Device modeling
> Electronic Devices and Circuits
> Digital CMOS Design
Academic Projects:
Project 1 #:
Title: Modified Compressor based Urdhwa Tiryakbhyam Multiplier
Description: In this project, introduces modified compressor based
multiplier architecture. This modified structure uses the 4:2 compressor
and 7:2 compressor architectures. In addition to that it uses Vedic
mathematics to get a high speed multiplication operation and low area
design. The design and experiments carried were carried out on a Xilinx
Spartan 3E series of FPGA and discussed about the results of area and
speed.
Project 2 #:
Title: Implementation and Analysis of Area and Delay of Array,
dadda, radix 2 Multipliers and various Adders
Description: This project deals with the Implementation and analysis
of different multipliers and adders with the help of Verilog HDL code in
XILINX. In this project, comparison of various types of multipliers and
adders are developed with respect to area and delay.
Journals Published
> N.Rajasekhar, Dr. T. Shanmuganantham, "A Novel 4 Bit Adder Based Urdhwa
Tiryakbhyam Multiplier" IJCSMC, vol 2, Iss. 10, Nov 2013.
> Maroju Sai Kumar and N. Rajasekhar. "Novel 16 Bit Adder design for Low
Power, Area and Delay" IJIRD, vol 2, Iss. 6, 2278-0211, June 2013.
> Maroju SaiKumar and N.Rajasekhar, "16-Bit High Speed Adder Design for Low
Power, Area and Delay Applications" Claro VLSI, Article ID "evl-1023-
2013",vol 4, iss. 6, 2013.
Software/Technical Skills
Programming Languages : C, Verilog HDL, VHDL.
Software's used : Xilinx 12.1 and 13.2, Tanner, Micro
Wind and MATLAB.
Packages : MS Office.
Operating Systems : Windows 98/2000/XP/2007.
Strengths
> Quick learner and good team player.
> Proactive and Driven by Disciplines.
> Good interpersonal and communication skills.
Personal Profile
Full Name : N RAJASEKHAR
Date of Birth : 14-07-1990
Nationality : Indian
Permanent Address :
H.NO:2-48-49-4-2/A,
Urban Colony,
Atmakur-518422(A.P).
Linguistic Ability : English, Telugu, Hindi,
Extra curricular Activities
> Participated in National level Paper Presentations and conference. 3rd
prize in National level Paper Presentation.
> Participated in national level Foot Ball.
> Participated in National Level Volley Ball.
> Event organizer in all school and college annual day functions and
other technical events.
Hobbies
> Playing Games
> Surfing Net
> Listening Music
Declaration:
I hear by declared that the above written particulars are true to the best
of my knowledge.
Place :
Date: (N.RAJASEKHAR)
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