Manager Manufacturing
Resume:
Sujit Saha
***.*******@*****.***
SUMMARY
Engineering Manager offering broad experience in manufacturing; domestic &
international factory start-up & improvement engineering in Semiconductor.
. Accomplished multiple industry leading projects: Pellicles in the early
'80s to improve sort yield by >25%, Intel's 1st factory in China, Intel's
1st metrics-driven product, process & equipment performance improvement
methodology using team-based structures.
. Conceptualization to implementation of a Class 1 state-of-the-art
automated wafer-cleaning area with many "firsts" within Intel. Improved
die yield by 5-10 die/wafer, reduced chemical cost by 40%; space
utilization improved 3x by consolidation of redundant cleans & steps.
Copied by other Intel sites. Received Divisional recognition. Dr Gordon
Moore personally came to see this project.
. Conceptualization to implementation of a Class 1 state-of-the-art
automated wet & dry wafer-cleaning area with many "firsts" within Intel.
Improved die yield by 5-10 die/wafer, reduced chemical cost by 40%; space
utilization improved 3x by consolidation of redundant cleans & steps.
. Designed a plating area with automated chemical delivery system that was
recognized as best in class by Dr. Andy Grove - CEO of Intel Corporation.
. Designed a HF filtration system for Oxide Etch with self-contained
temperature control and pump isolation.
. Integrated Intel's 1st automated chemical delivery system to a fully
automated wet processing line.
. Broad experience in hazardous waste collection and disposal including
solids, liquids - pH adjust and HF treatment, solvent collection system.
Setup a hazardous waste clean and disposal facility for a large
semiconductor campus. Included solid waste disposal and collection of
acid (HF) and solvents. Challenged recommendations of a highly reputed
Environmental Consultant to build an effluent fluoride treatment
facility. Changed wet processing to HF filtration and low DI water using
clean equipment to reduce cost and waste generation. Effectively a "zero"
discharge facility. Waste treatment benchmark team member to IBM East
. Startup experience of 4" thru 8" wafer fabrication including 8" optical
wafer fab. Greenfield startup of backend assembly/test manufacturing in
Asia.
. Led large multicultural, multi site matrix teams of managers & groups
leaders for critical projects like Y2k (7k equipment) & factory startup
(15k work breakdown structures) using Primavera and MS Project scheduling
tools.
. Broad experience in startup and operations management including equipment
engineering, manufacturing, planning and facilities engineering.
. Trained in Intel silicon product lifecycle) similar to SCRUM, Phase Gate,
Agile), burn-in, test methodology & packaging technology (BGA, SCSP,
FSCSP, TSOP, uBGA.). NPI thru EOL product planning including product
transfer from Intel validation lab to internal & contract manufacturing
in Asia.
. Implemented TPM & Lean methodologies in development & high volume ramp.
Trained in TOC; TPM/Lean/TPS, FMEA, DMAIC, 7-step problem solving, etc.
Benchmark team member: US (Ford Motors) & Japan (NEC, Fujitsu,
Mitsubishi).
. Member of 2 (Intel US & Intel China) ISO implementation core teams and
certified ISO auditor.
EDUCATION
. MS in Industrial Engineering, Texas Tech University, Lubbock, Texas
. PhD/MBA coursework, Texas Tech University, Lubbock, Texas
. BS in Mechanical Engineering, Rajshahi University of Engineering &
Technology, Bangladesh
PROFESSIONAL EXPERIENCE
Apple Inc., Cupertino CA
2010 to 2012
Technical Program Manager
. 5 cleanrooms in China were built under my guidance &10 cleanrooms went
thru audit & post audit remediation under my supervision. Saved $1.2M
(20% of total) from BOM gaps. Design change proposal to reduce cleanroom
space for iPad assembly by 75% using local isolation.
. Designed a class 10k cleanroom, material handling and cleaning process to
deliver particle free antenna modules to final assembly.
. Designed pack automation of iPad & iPhone. Saved $10m+ for iPhone 5 and
using "should cost" analysis and challenging & re-negotiating contract
pricing. 2 prototype solutions delivered on time despite iPhone design
change 1 month before shipment. Worked with automation design houses in
Asia, Europe, and US & CANADA.
. Exposed to manufacturing of metal housing, gaskets, cameras, final
assembly, LCD, antenna, speakers/receivers, test/burn-in and pack & ship.
Western Digital Magnetic Head Operation, Fremont, CA
2008 to 2009
Program Manager - Fab 8" Conversion & ramp
. Converted an existing 6" wafer fabrication line to 8" consisting of over
60 new tools. Established pilot process line in 3 months. Consistently
exceeded development wafers moves & pilot equipment uptime and
utilization goals. Managed 3 direct reports.
. Set accurate min-max, safety stocks for direct/indirect (spares, targets,
chemicals) materials for all 8" equipment.
. Worked closely with IT group to ensure data automation and equipment
station controllers readiness to support ramp.
Marvell Semiconductor, Santa Clara, CA
2006 to 2008
Capacity & Manufacturing Systems Manager
. Managed capacity & capability transfer from Intel to Marvell factories in
Asia in 3 months without any impact to product shipments.
. Completed capacity/capability transfer from Intel to Marvell in 3 months.
Sourced test & back-end manufacturing equipment from inside/outside Intel
for a seamless start-up and ramp at Marvell facilities in Malaysia,
Singapore and Arizona. Completed without supply line impact.
. Operations team member owning factory & product roadmaps, division level
capacity and deployment. Interfaced with the business units, factory &
contract manufacturers for tactical operational decisions; Inventory
management & build plan response.
Intel Corporation, Santa Clara, CA
1984 to 2006
Operations Manager, Mobility Group (2004 - 2006)
. Managed multi-chip packaging & manufacturing methodologies & integration
of roadmap changes into the factory network. Developed & maintained
operations systems & business processes for long range plan;
. Member of NPI forecast team & corporate roadmap team; improved NPI thru
final assembly & test business process & parameter data quality;
increased validation lab test capacity by 2x.
. Transfer leader for pilot products from Intel validation labs to Asian
high volume assembly/test manufacturers. Maintained continuous cost
reduction opportunities thru BOM change &/or moving to lower cost Geos.
Ensured NPI collaterals supply: probe cards, tester boards, burn-in
boards, lead-frames, etc
. Leader of task force for 100% external manufacturing of $600m business
group: die thru assembly/test & burn-in. Generated RFQ, invited proposals
from all major Asian contract manufacturers & used COO (cost of
ownership) models for supplier selection.
Operations Program Manager, Optical Products Group. Fremont, CA
. Pilot product startup, US manufacturing support & transfer to Asia for
high-volume manufacturing of 2 transponder products. Managed pilot PCB
assembly development at Fine Pitch, Fremont & high volume manufacturing
transfer to Jabil in Malaysia.
. Benchmarked Intel desktop product development methodology & best-known
methods for the Wireless Network Group (Centrino product group) to reduce
time to money using NOBI/ZOBI & early test screens.
Manufacturing Engineering Manager - Photonic Technology Operation,
SanJose,, CA
. Start-up of Intel's 1st Optical wafer fab, assembly & test facility.
Hired, trained & certified all direct operators/technicians. Managed a
group of 15 exempts & non-exempts in IT, equipment engineering,
materials, planning & manufacturing operations. Owned annual AOP for H/C,
operations budget & capital.
. Developed manufacturing operations specs, equipment specs & maintenance
plans. Setup service contracts, calibration schedule, on-site consign
inventory of spares & consumables. Setup hazardous chemicals & waste
storage & disposal system.
. Implemented a site-wide ergonomics program with close partnership with
site/corporate safety & EHS. BKM s adopted by other Intel sites safety
teams.
. ERT, Safety & ISO 9001 team member & certified ISO auditor.
Manufacturing Engineering Manager. Intel Santa Clara & Intel Philippines
. Managed an install/quall duration study of multiple process equipment
from move-in/set to production readiness using a consulting company.
Results were used in duration streamlining for shorter time to money.
. Flash PPSC (Product Platform Steering Committee) coordinator for virtual
flash network including wafer fab, business group, and manufacturing to
align to strategic & tactical roadmap.
. Developed business process to close installed capacity vs. requirement
gaps by accelerating response to demand cycle. Changes approved Fab Sort
Manufacturing management (senior TMG managers).
Assembly Test & Sort Manufacturing Y2k Program Manager
. In 9 months led team from "most behind" to "most ahead". Recognitions
from Dr Grove & Dr Barrett.
. Matrix managed 16 managers & group leaders. My team owned testing, bug
fix software development & deployment for 7k+ equipment in 5 worldwide
factories in 5 time zones.
. Program completed 3 months ahead of schedule well within $70m budget.
Reported to Intel VP.
. Chaired change control board & led worldwide audit team. Passed external
auditor audit with zero gaps.
Industrial Engineering Manager. Intel Technology China. Shanghai, China
. Hired, trained & transitioned management to local Chinese staff 6 months
after factory startup. Co-owned factory qualification, process
qualification & transfer of a plastic TSOP product. My team owned master
schedules using Primavera with 15,000+ WBS in the schedule. Owned
capacity planning, layouts, equipment roadmap, and equipment installation
& support infrastructure. Program completed 3 months ahead of schedule &
under budget including ISO certification. Received multiple recognition
awards.
. Dr. Andy Grove recognized the automated package plating lab area design
as the "best" he had ever seen.
TPM Program Manager. Santa Clara, CA
. Set-up a state of the art "parts clean" facility for a 200mm/0.26 m
process technology.
. Managed a PM (preventative maintenance) effectiveness task force to
maximize output from PM quality, speed and effectiveness.
. Application of TPM (total productive maintenance) methodologies to a new
0.26um/200mm technology (Intel's 1st 200mm facility) and concurrent
startup & ramp of Intel fabs in New Mexico and Ireland. Developed
computer models to translate high-level technology goal into
station/module improvement team goals for capacity, reliability, line
yield and defects/pass. This was Intel's 1st "Metrics Book" which
shortened time to money and exceeded all past track records. Goals also
used for equipment purchase specs, another Intel 1st.
. Developed "Speed & Availability" models for all process equipment. These
became technology goals for three of Intel's then latest 200mm fabs.
. TPM/TPS/Kaizen benchmark team member to Ford Motors in Detroit, NEC,
Mitsubishi and Fujitsu in Japan.
. Initiated and implemented a "95% in '95" line yield improvement program
to increase line yield from historical 80% to 97% using by driving floor
level ownership. Received Divisional recognition
Industrial & Manufacturing Engineering Manager. Santa Clara, CA
. Conceptualization to implementation of a Class 1 state-of-the-art
automated wafer-cleaning area with many "firsts" within Intel. Improved
die yield by 5-10 die/wafer & reduced chemical cost by 40%; space
utilization improved 3x by consolidation of redundant cleans & steps. BKM
s copied by other Intel sites. Received Divisional recognition.
. Initiated and implemented a "95% in '95" line yield improvement program
to increase line yield from historical 80% to 97% using by driving floor
level ownership. Received Divisional recognition
. Managed a capital budget of $25M including annual AOP. Owned qtrly
capital/expense plan/actual reviews; capacity & capability justification
& review with VP. Managed a full time budget planner who tracked all
commits vs. actual. Headed qtrly review with site finance and divisional
controller and submitted required monthly/qtrly status & variance
analysis.
. Personally convinced Dr. Gordon Moore to reverse ESM decision to not
convert the fab to150mm: a $200 - 400M project.
. Trained by Dr. Deming in Deming Philosophy as practiced by Japanese
manufacturers.
AWARDS
. Divisional Award for "Successfully implementing SAP in record time"
. Divisional Award for "1st successful PTO Site Shutdown Execution"
. Photonics Technology Operation Award for "Supporting Emergency Response
Team"
. Photonics Technology Operation Award for "6 week pull in of the Fab Start-
up Schedule"
. Outstanding Achievement Award for "Year 2000 Program" from Andy Grove &
Craig Barrett
. Divisional Award for "Bond Pad Corrosion Solution"
. Divisional Award for "Root cause Identification and Fix of N2 Cabinet
Particles in less than a Week"
. Divisional Award "For Flawless Execution of Surplus Equipment Reuse
Savings of $4.3M
. Divisional Award for "Dedication and Hard work in Getting Primavera
Executed"
. Achievement Award "For Excellent Leadership in Driving D2 Line Yield and
Developing a Pareto based Improvement Methodology for Line Yield that
Stimulated Factory Floor Ownership"
. Divisional Award for "Teamwork Exhibited in the Highly Successful
Decommissioning of Fab 1"
. Divisional Award "For Implementing a State-of-the-Art Wafer Cleaning
Facility"
PUBLICATIONS
. "EDO Improvement Ratio as a Prioritization Methodology for Factory
Improvements", ASMC (Advanced Semiconductor Manufacturing Conference)
SEMI-IEEE, Cambridge, Massachusetts.
. "PM Effectiveness as a High Leverage Output Improvement Methodology,"
ASMC.
. "EDO Improvement Ratio as a Prioritization Methodology for Factory
Improvements", IMEC (Intel Manufacturing Excellence Conference), San
Diego, California.
. "PM Effectiveness - The Indy 500 Way", IMEC, San Diego, California.
. "Application of Sematech Defect Model to a 0.6(m Process Defect
Reduction," ASMC. SEMI-IEEE.
. "Iterative Capacity Analysis in a Ramping Factory," IMEC, San Diego,
California.
. "Application of the Sematech Defect Model to P852 and TPM," IMEC, San
Diego, California.
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