SOWMYA MOOLCHANDRA RAJPUT

*** ****** **, ********, ** 07029 347-***-**** ac9wg7@r.postjobfree.com linkedin.com/in/sowmyarajput

Hardware Engineer with 1-year experience seeking a Full Time Job Starting July in the field or Digital Design and RTL/Verification. Effective communicator and team player with excellent interpersonal and analytical skills, consistent academic record, willing to learn and adapt to new opportunities and challenges.

Education

New Jersey Institute of Technology, New Jersey, USA MAY 2019

Master of Science in Computer Engineering (Digital Design and Computer Architecture) GPA: 3.5/4.0

University of Mumbai, Mumbai, INDIA AUGUST 2016

Bachelor of Science in Electronics Engineering GPA: 3.5/4.0

Skills

Concentration and relevant courses:

VLSI Design, Computer System Architecture, Semiconductors, Embedded Computing Systems, Digital Signal Processing, BioRobotics, Computer Networking, Advance Microprocessor Systems

Programming Languages: C, C++, Verilog, VHDL, Python, C#

Tools: MATLAB and Simulink, OrCAD, Altium, HSPICE, Xilinx, Altera, ModelSIM, Mentor Graphics, PrimeTime, Quartus II, Unity 3D

Hardware and Operating Systems: Linux (Ubuntu), Arduino Uno and Mega, Raspberry Pi 3, Arm Cortex M0 and M4

Communication Protocols: I2C, SPI, UART

Micro-Computer Architecture, SRAM, DRAM, FLASH, Cache and PCI, PCIe.

Working knowledge of Op amp circuit design, filter design, communications, digital sampling theory, and digital circuit design utilizing microcontrollers and digital signal processors.

Logic and Gate Level design and synthesis, Static Time Analysis, timing closure of setup and hold time.

Academic Projects

Design and Implementation of Sensor-Based Car Parking System using Altera DE2-70 FPGA board

Developed the Finite State Machine (FSM) model of a 4-digit password protected secure car parking system and used sensors in parking lots to indicate an available spot to the user. Interfaced the system with the Altera DE2-70 board using VHDL coding language.

A Parallel Algorithm and Architecture for Object Recognition in Images using VHDL

Implemented a parallel algorithm that uses tree pattern matching to recognize and match a subject string to a given pattern string. The algorithm was implemented as a single VLSI chip operating at a clock speed of 333MHz.

Design of 8- bit Linear Feedback Shift Register utilizing the n-well 0.18 µm CMOS process

Designed the chip for an 8-bit linear feedback shift register and drew the CMOS transistor circuit diagram using the schematic editor and using the transistor realizations of ordinary CMOS gates. Generated the mask layouts using Mentor Graphics EDA tools, performed speed calculations describing the critical path and stage optimization, total power dissipation, lowest clock operational frequency while optimizing the device size.

Design of a Cryptographic Coprocessor using Altera DE2-70 FPGA board

Designed and implemented a coprocessor using VHDL, consisting two register files to store the incoming and the encrypted data, and a combinational logic made up of a nonlinear lookup unit, an ALU, shifter and a control logic.

Functional Verification Environment for I2C Master Controller using System Verilog

The RTL behavior of the I2C Master Controller is verified using System Verilog in Mentor Graphics tool. The verification environment includes the constrained randomization, functional coverage and code coverage without any data loss in transmission.

Professional Experience

INTERN, Technobotics, Mumbai, India SEPTEMBER 2015 - OCTOBER 2016

Design Quadcopters with face-detection capabilities using Voila-Jones algorithm.

Develop technical design specifications for hardware design, schematics, and board design.

Perform the procurement of the equipment, assembly and testing for design flaws.

Owned the execution and logistical support for workshops on Robotics at multiple locations across Mumbai, India.

INTERN, Nuclear Power Corporation of India Ltd., Mumbai, India JULY 2015 – AUGUST 2015

Develop design specifications and schematics for electrical prototypes.

Perform synthesis and place & route using the OrCAD package including OrCAD Capture CIS, OrCAD PCB Router and Allegro PCB Designer.

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