Sign in

Engineer Design

Cairo, Cairo Governorate, Egypt
May 30, 2019

Contact this candidate


Mina Magdy Badir

Hardware Modeling Engineer

Address: * **. ***** ****** *****, El-Wehda El-Arabya, Shoubra, Egypt, 13766. Tel: +201********* Email: LinkedIn: in/minamagdy0 PERSONAL SUMMARY

Seeking a challenging Job, where the technical, academic and soft Skills can be utilized, developed and to be beneficial to the place working in and help to achieve the dream of adding a contribution to the technology world and looking for a challenging opportunity in one of the leading companies in Electronics Engineering generally, and specifically in Computer Design companies.


Abdelfattah Munir, Mina Magdy, Samer Ahmed, Sherouk Nasr, Sameh El-Ashry, Ahmed Shalaby "Fast Reliable Verification Methodology for RISC-V without a Reference Model", Microprocessor/SoC Test, Security and Verification

(MTV18), Austin, Texas, Dec 2018.


Hardware Modeling Engineer - Mentor Graphics, A Siemens Business, Cairo, Egypt April 2018 - Current

• Develop software Models for Hardware devices/Cores.

• Using QEMU to develop Core Models.

• Create SystemC TLM models to create Virtual Platforms.

• Test the models using existing processor models.

• Verify the models' functionality versus behavior model using SystemC.

• Execute the implementation/test plan and apply unit testing/debug.

• The models are targeting ARM, RISC-V and PPC Multi-Core architectures and other models/peripherals for examples: DMA, Timers, UART, SPI/QSPI, PCIe, Caches, I2C, and DDR Controller. TECHNICAL SKILLS

VHDL/Verilog UVM SystemC/TLM C/C++

System Verilog Embedded Systems Scripting FPGA PROFESSIONAL SKILLS

• Experienced in communication Protocols.

• Competent in debugging code at a hardware level. PERSONAL SKILLS

• Prioritization the individual workloads according to deadlines.

• Ability for self-education through E-learning.

• Working Under Pressure.


Information Technology Institute - Ministry of Communications, Giza, Egypt October 2017 - June 2018 Digital IC Design, 9-month specialized Diploma program in Digital IC Design. The program was under the sponsorship of Synopsys and provides full versions of Synopsys Tools for design purposes. Graduation Project: Automated UVM environment for RISC-V verification.

Specification Extraction for RI5CY Processor.

Conducting a Verification Plan.

Conventional Test bench for early stage verification and simulation.

Sequence Layering for Constrained-Random testing and Direct testing Stimulus.

Implementation of Scoreboard model as well as assertion based checkers.

Implementation of Coverage model.

Faculty of Engineering - Ain Shams University, Cairo, Egypt September 2012 -July 2017 BSc, Electrical, Electronics and Communications Engineering.

Distinct with Honor degree [90.2 % - Ranked 7 out of 100].

Graduation Project: MEMS-based IR spectroscopy for food analysis for IoT Applications [Excellent grade]

[Supervisors: Dr. Diaa Khalil, Dr. Yasser Sabry] (2nd Place - IbTIECar IoT [Smart Buildings Track]). PROJECTS

Design of an Internet of Things [IoT] system to monitor moisture and temperature by using Pico Blaze soft-core processor on Artix-7 FPGA that communicates with PC.

Conducting Verification plan and implementation of a verification environment using System Verilog and UVM for AHB SoC and AXI4-lite buses.

Design for a queuing system in a bank using two sensors to detect entering and leaving the queue.

Design for temperature monitoring system using UART communication between 7-segment and PC.

Full Structural Design for a security system.

Extracting Standard Cells Characteristics used for Carry Look-ahead Adder using Perl Script. TRAINING AND INTERNSHIPS

Mentor Graphics training in Analog IC design flow.

Summer Internship at Si-Ware in OMTD.

Doulos Modular SystemC and TLM 2.0.


Teaching Assistant, Verilog and FPGA Workshop, iHub, Ain Shams University, Egypt (Jan 2018). References available upon Request

Contact this candidate