Design Engineer Project

Abhishek Rai

*************@*****.***, 897*******

Sullia-574212, Karnataka

Career Objective

To work in a professional work driven environment as a Physical Design Engineer where I can get a platform to learn and deal with advanced technologies that would improve my knowledge and skills while fulfilling organization goals.

Core Competency

Familiar with ASIC design flow (RTL to GDSII).

Performed efficient timing aware and congestion driven macro placement during Floor planning, Power planning with IR drop analysis.

Acquaint with the Static Timing Analysis (STA) concepts: OCV, CRPR, the effect of clock skew on timing, fixing setup and hold violations.

Accustomed with reliability issues like EM and Antenna effect. Signal integrity issue like X-talk and DFT issue like Scan chain reordering.

Good knowledge of Digital Circuits, Transistor Theory and Circuit Analysis.

Analysis and interpretation of TCL.

Education Details:

Advanced Diploma in ASIC Design - Physical Design

RV-VLSI Design Center

2019

M.TECH in Digital Electronics and Communication

Dayananda Sagar College of Engineering, Bangalore with CGPA-8.81 2018

Bachelor Degree in Electronics and Communication

Canara Engineering College, Mangalore with 60.6%

2016

PUC in PCME

Sharada PU College, Mangalore with 78.12%

2012

SSLC

Pragathi High School, Kaniyoor with 77.76%

2010

Domain Specific Project:

Block Level Floorplanning and Powerplanning:

Description Implemented block level design for Lakshya subsystem in 40 nm technology. Specifications Supply voltage: 1.1 V, IR drop: 5% of the operating voltage, Standard cell count: 38887, Hard macros: 34, Frequency of operation: 1 GHz, 5 clocks, 7 metal layers.

Tools Synopsys IC Compiler

Block level Placement and Clock Tree Synthesis:

Description A timing driven and legalized placement of standard cells thereby ensuring good routability. Built a Clock Tree to get an optimized skew, reduced timing violation, design rule violations and minimum WNS, TNS.

Tools Synopsys IC Compiler

Static Timing Analysis for various Timing paths:

Description Interpreted Setup and Hold timing reports. Dealt with false paths and half cycle paths. Tools Synopsys Prime Time

Challenges in Project Implementation:

Placement of macros during Floor planning using dataflow diagram of the design and pin placement.

Creation of efficient power mesh within the IR drop limit.

Inspection of floating shapes for metal layer and fixing through defining routing blockages over hard macro cells.

Scrutinized the congestion map to determine congestion and worked on its alleviation.

Accomplish the legalized placement of standard cells, high effort placement optimization during placement.

Timing analysis after each stage of APR flow to identify the type of violations and its sources.

Usage of timing exceptions such as false path and multicycle path. Setting up multicycle timing exception on particular pins to meet the timing requirement. Computation of setup and hold slack. M.Tech Academic Project:

Rainfall Estimation Using Polari metric Weather Radar by Measuring Reflectivity In the above work carried out at Radar Development Area, ISRO by signals obtained from dual- polarisation radar at Chirapunjee, measurement of rainfall is done considering the drop shape of raindrop is considered to filter out the non-metrological components by using the integrated differential reflectivity has shown improvement in rainfall estimation and also provides the characteristics of the metrological components.

B.E Academic Project:

Study of Neurological Disorder Using EEG to Find ASD and ADHD Our proposed work with the help of Mallikate Neuro Centre and St. Agnes Special School can be a useful tool for doctors and technicians to predict the percentage of ASD and ADHD easily. Was done by extracting the non-linear features in EEG and using the Knn-Classifier for classification has provided 99.45% accuracy.

Certification

Won 1st place for paper presentation on “Classification of EEG Signals Using the Wavelet Transform” at National conference IEEE student chapter at PSNACET, Dindigul, Tamilnadu.

Presented a paper on “Characterization of EEG signals to study Autism Spectrum Disorder” in Impulse-15.

Presented following paper “A survey on design and analysis of robust IOT architecture, A survey on Facial feature extraction techniques for automatic face annotation, Review of Interoperability approaches in application layer of IOT” in the 2nd National Conference on Sustainable Emerging Intelligent Technologies (SEITCON-17).

Published a paper on “Rainfall Estimation Using Polari metric Weather Radar by Measuring Reflectivity” in IRJET (p-ISSN: 2395-0072)

Internship/Course

BHEL-EDN (2 month): Electric Traction, PCB Design and Solar Panel design.

MRPL Mangalore (15 days): Automation, Control Instruments.

Perceived project at Radar Development Area, ISTRAC, ISRO (8 months) on “Rainfall Estimation Using Polari metric Weather Radar by Measuring Reflectivity”.

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