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Engineer Design

Location:
India
Posted:
March 07, 2019

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Resume:

Vasvi Patel

Banglore, India ac8pam@r.postjobfree.com

DOB : 30/10/1990 +91-903**-*****

+91-701*******

SKILLS

Verilog, System Verilog, Basics of UVM, Perl, Multisim, MATLAB, Xilinx, Basic C Programming EDUCATION

M.E

(Electronics and Communication)

Gujarat Technological

University

Hasmukh Goswami College

of Engineering, Ahmedabad

June-2015

CGPA

8.24

B.E

(Electronics and Communication)

Gujarat Technological

University

Government Engineering

College, Modasa

June-2012 CGPA

7.04

Diploma (Electronics and

Communication)

Technical Education

Board

Govt.Poly.For Girls,

Ahmedabad

June-2009 72.00%

S.S.C G.S.H.S.E.B J.N.Balika, Ahmedabad March-2006 86.86% PROJECTS UNDERTAKEN TOOLS USED : QUESTA SIM

1. Memory Controller Functional Verification using System Verilog Duration: 5 months

Description:

o Design supports SDRAM, SSRAM, Flash & Synchronous Chip select devices. It has support for 8 chip selects. It also supports flexible timing configuration for different memory types. Created testbench using SV to generate scenarios targeting all types of supported memories for different possible combinations & different sizes supported As part of this design verification.

Responsibilities:

o Listing down features, scenarios

o Developed monitor, reference model & checker as part self checking testbench implementation. 2. AXI VIP Development and validation using AXI slave VIP Duration: 3 months

Description:

o AMBA AXI protocol for on-chip communication supports high performance, high frequency system design.AXI is suitable for memory controllers with high initial access latency. It also supports separate read and write data channels that can provide low-cost Direct Memory Access.Same time it provides flexibility in the implementation of interconnect architectures.

Responsibilities:

o Developed BFM, Generator models for test case scenarios targeting AXI protocol features. o Validating AXI VIP using AXI slave model.

3. Asynchronous FIFO design and verification using Verilog 4. Interrupt controller design and verification using Verilog 5. SPI controller design and verification using Verilog 6. WDOG timer design and verification using Verilog 7. Vending machine design and verification using verilog TRAINING / COURCES undertaken

o Successfully completed six months Verilog and Systemverilog course at VLSIguru Training Institute, Bangalore o Completed online courses on Verilog HDL programming with Xilinx ISE & Spartan nexys FPGA and VLSI-Essential concepts

ACHIEVEMENTS

Published 2 Papers on Image Fusion for Underwater Images using Curvelet Transform Image denoising, Gaussian Filter, Mean Filter, Weiner Filter, Comparison, Fusion, Simple Average Method, Average method using Curvelet Transform, PSNR, MSE, MAE, Correlation ; during 2nd National Conference on Emerging trends in engineering and technology & Management at Indus Institute of Technology and a, International Journal for Scientific Research & Development, ISSN : 23210613, 2015.



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