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Engineer Process

Hillsboro, OR
December 01, 2018

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Jerry Albright

Home 503-***-**** cellular-503-***-**** 3045 19th Ave apt #32

Forest Grove, OR 97116

OBJECTIVE: an engineering position that will leverage my skills and experience

EDUCATION: Pacific University, Forest Grove, OR

B.S., Physics/History, 1994 University Honors, Politics and Law Forum, Yearbook


Strong analytical ability combined with extensive experience in problem solving, conception and execution.

Hard-working, reliable; able to collaborate in a team enterprise.

Accurate, assertive, adaptable with excellent verbal and written skills.

Self-starter who works well independently and as part of a team with a proven ability to multitask.

COHE inspector

Training new technicians and engineers in current process development, equipment sets, and specialized software setups.

With 24 years of experience working in Intel’s Defect Metrology including 15+ in 300 mm fabs I have first hand knowledge and experience with all many semi-conductor metrology tools from install/qual to production.

Vast experience with multiple operating systems and software packages:

•Windows •MacOS •DOS •UNIX •Linux

• Microsoft Office Suite •Adobe PhotoShop •Adobe PageMaker •Klarity expertise

Network setup and configuration: I owned networking/data transfer setup for new PTD dark field tools in D1C& D1D

Experience with building, customizing, and troubleshooting PC systems.

Defect Metro floor operations: expertise in all fab operations and systems


Developed and presented 8+ classes on Workstream/ELF BKM’s for the Defect Metrology area.

Writing inspection recipes for brightfield(KLA 213X) and darkfield inspection systems

Part of team which won Intel’s 1995 Portland Technology Development Design of Experiments award. The award was awarded for using statistical models to optimize the capture of real defects on the KLA.

Member of the 1264 MES lotfile user group which defined and tested the new fab execution system

Initiated yield monitoring of Intel's copper process. This involved preliminary engineering work with the defect tools, choosing the points in the process which would be monitored and setting up the operations to run these monitors.

Assisted in startup of Intel’s first 300mm Fab, D1C.Assisted in startup of Intel’s most advanced Fab D1D/D1X

Of course this is just a brief list of my accomplishments and primary abilities/strengths, I can give detail on request of course.

Intel Corporation work history Hillsboro, OR August, 1994~November 2018

• Intel Defect Metrology Systems engineering tech specialist: May 2015-November 2018

Owned over 130 specifications documenting defect classification, TW maintenance, and system control procedures. Generating hundreds of new process operations each year, along with associated route flows. Whitepaper authoring. SPC modeling, ISO requirements and documentation; coordinating yield readiness for New Product Introductions

• Defect Metrology Equipment engineering technician (Intel-PTD) January 2014 to May 2015: primary duties of this custom made position included, but were not limited to specification, PM checklist, and RFC support for all defect metrology toolsets(KLA brightfield/darkfield/Macro inspection systems, Applied and KLA-Tencor review SEMs, Hitachi inspection and review systems. Engineer training. Advanced tool support tasks

• Defect Metrology Technician (Intel-PTD) January 1995-December 1997, February 2000-January 2014

Running regular monitors on key layers throughout the development/production line. Responding to issues with the equipment(KLA’s, Tencor Surfscans, Amray SEM/EDS) owned by the Defect Metrology group at nights and other off hour shifts. Performing key engineering work to detect defects. Authored Specs, BKM’s, and RFC’s, tool networking, PM setup and execution, put together 300mm wafer archiving process, etc. Again these is just my primary duties, I can expand at length. Tool installation on KLA 213x inspection systems, Tencor AIT systems, and 300mm brightfield and darkfield inspection systems as well as ORL inspection/review tools.

• Integration Technician, December 1997 - February 2000

Overseeing the process for BackEnd(BE) pathfinding material. (Pathfinding being the name given to the group working two process generations into the future). Duties include, but not limited to: Ensuring experiments keep moving through a shared fab. (Shared with another process development cycle); SEM&FIB&EDS work to analyze the effects of these experiments; Etest analysis, and shipment of wafers offsite to vendors for processing or analysis(TXRF). Lot file setup experience for Full loop lots and shortloop experiments. SMR route creation and editing proficient.

• Intel Technician (Oregon Prototype Production Systems{OPPS} )August 1994-January 1995

assembling and debugging PC motherboards, including Final inspection, solder/de-solder, test, and board configuration.

• Amazon Fulfillment center associate: (November 2016-March 2017)seasonal position sorting packages and building pallets for shipment to customers

• Walmart Cap2 Associate-Fresh:(May 2017-present) Produce associate responsibilities included stocking fruits and vegetables, product rotation, culling damaged/spoiled produce, cleaning, using pallet-jack


Tuyen Tran Yield Group Leader Intel-PTD 503-***-****

David Shykind Senior Process Engineer(Intel Corp) 503-***-****

Josh Symonds Process engineer(Intel Corp) 503-***-****

Sam Sweeney Owner: Country Heritage Farms 503-***-****

Additional Available upon request

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