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Engineer Design

Hoboken, New Jersey, United States
August 12, 2018

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PARDHU KOMMINENI Ph: 909-***-**** /


•Research experience in ASIC Verification

•Experience in Infotainment system (IVI), mobile testing and Configuration Management activities

•Collaborated with users and Information Systems group to implement and test applications.

•Mobile Data Entry and RF technology.

•Hands on experience installing hardware (PC’s, Clients, Printers, Network systems), software and operating systems.

•IT support with network backup and recovery procedures

•Ensured implementation of all standard operating procedures for efficient business operations

•Remote support tools to quickly diagnose software problems, decreasing down time.

•Experience in writing RTL models in VHDL, Verilog

•Experience in using industry standard EDA tools for the front-end verification


M.S. in Computer Engineering Aug 2017

California State University, Fullerton, CA


Logic Design in Nanotechnology, Low Power Digital IC Design, Mixed Signal IC Design, VLSI Testing and Design for Testability, Advanced Nanoelectronics, Systems and Software Standards and Requirements.

PG-Diploma in VLSI May 2015

Center for Development of Advanced Computing(CDAC), Pune, India

B.Tech. in Electronics and Communication Engineering Apr 2014

Jawaharlal Technological University, Kakinada, India


Computer Skills: Spreadsheet (Excel), MS Office.

Languages: C, Embedded C, Perl, Python

Hardware Description Language: Verilog, VHDL, System Verilog

Environment: Linux, Windows

EDA Tools and Simulators: Synopsys VCS, Waveview, Hspice, Xilinx ISE, ModelSim

Others: Mat lab, Simple scalar, Code Composer Studio

Mathematics & Statistics: Experimental Design, Descriptive and Inferential Statistics, Linear Regression.

Soft Skills: Oral & written communications, Problem solving, Attention to detail


Current project:

Automotive Infotainment and Telematics; Testing Jan 18 – Present

Synapsis, Texas

Involved in Compatibility Testing, Usability Testing, Regression testing, Functionality testing of IVI.

Performance testing and System testing.

Implemented standard operating procedures.

Arm coresight architecture (soc) Oct 17 - Dec 17

Remote, India

Tools and Technologies: Synopsys VCS, System Verilog

Coding C and SV for Configuration of Trace components and Bus Monitors.

Generating trace and verifying Trace components.


Research Intern under Prof. Aaron Stillmaker: Aug 16 – May 17

•Research on many core processor arrays in mass, example kilo core processor from UC Davis.

•Research on power gates in large digital system for optimal usage.

VLSI lab: Assistant Oct 15 – Aug 16

•Developed layouts of high performance Full adder of mirror design style, D- Flip flop & Scan Flip Flop

•Tested these layouts performance like functionality and delay using Hspice and Waveview

•Designed and further developed memory techniques for intelligent systems under the guidance of Prof. Kiran George.

Student Technology Services: Administrator Jan 16 – Nov 16

•Assisted students and other members of the College community to access Student Support Services.

•The production of documents and reports etc. using the full Microsoft office applications including Word, Excel, PowerPoint and diary management.

•Installations of computer software and hardware; maintain complete inventory of computers and related hardware.

•Assisted IT support with network backup and recovery procedures.

•Develop, implement, and monitor information technology quality assurance standards.

R&D lab at CDAC: July 14 – May 15

•Interned in the projects of high speed networking for PARAM supercomputers.

•Designed basic building blocks for host interface architecture and verified.

•Designing involved RTL coding in VHDL, synthesis and verification

Defence Electronics Research Laboratoty(DLRL): Research Intern Jan 14 – Apr 14

Hyderabad, India

•Developed a square patch antenna for low area reception.

•Proposed a new technology - Reflective invisible shield for insects.


21X21 booth multiplier: Summer 2017

Tools and Technologies: Cadence, Hspice, WaveView

•Designed in schematic form using booth 2 algorithm

•Compressors and carry look ahead adders are used to reduce the delay and power

•Verified the functionality using Hspice simulation

1280-bit SRAM: Spring 2017

Tools and Technologies: Cadence, Hspice, WaveView

•Designed 128-word SRAM with a word size of 10 bits using 6T cell

•Designed conventional column and row decoder and performed manual placement and routing

•Calculated worst case write and read time delays are 307ps & 487ps respectively

Design of a 16-bit customizable microprocessor on Nexys 4 Spartan FPGA Board: Fall 2016 Tools and Technologies: Nexys 4 Spartan board, Xilinx ISE, Adept, Verilog

•Developed 16-bit microprocessor with 12-bit address using Verilog code

•Instructions given through keyboard interfaced with Nexys 4

•Verified results on VGA monitor and displayed instructions in debug mode

Cache Design Optimization: Spring 2016

Tools and Technologies: Simple Scalar simulator, Perl

•Verified different Cache parameters such as Cache levels, Size, Associativity, Block Size & replacement policies

•Used PERL script to simulate various combinations of these parameters for 4 benchmarks of Alpha microprocessor

Memories: single port memory (64X32) and dual port memory (64X32) Fall 2015

Designed RTL in Verilog by using structured approached and synthesized both single port and dual port memory for 0.5-micron technology

Verified their functionality & simulated them on Verilog simulator modelsim

Automation: Written Script for both single port and dual port in Perl.

BIST: single port memory BIST (64X32) Fall 2015

Designed RTL using Verilog and synthesized both single port and dual port BIST for 0.5-micron technology

Verified their functionality & simulated them on Verilog simulator modelsim

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