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Computer Engineering

Location:
San Diego, California, United States
Posted:
February 16, 2018

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LinkedIn: www.linkedin.com/in/rutvi-tripathi

Name: Rutvi R Tripathi

Email: ac4h5p@r.postjobfree.com

Address: ***** ****** ****, *** **, San Diego 92126

Contact: 919-***-****

Professional Summary

Computer Engineering graduate aspiring to build a career in the field of Physical Design and ASIC Design - Available from January 2018.

Education

Masters of Science Computer Engineering, ECE

GPA: 3.2/4.00

North Carolina State University

Graduated: December 2017 Raleigh, NC

Bachelors of Engineering Electronics & Communication Engineering

GPA: 8.2/10.00

Gujarat Technological University

Graduated: May 2015 Vadodara, Gujarat

Technical Skills

Programming Languages-- Verilog, System Verilog, C, C++.

Tools, Platforms, and Skills-- RTL Design, OOP, Static Timing Analysis, Clock Tree Synthesis, Circuit Analysis, PD Flow, Timing- Constraints, Low Power Design, Model Sim, Synopsys Design Compiler, Cadence Virtuoso, MATLAB, HSPICE, Windows, Linux.

Industry Standard Fabrication Process-- JT Baker cleaning, photolithography, LPCVD, Ion Implantation, Reactive Ion Etching, Rapid Thermal Annealing, DC sputtering, Boron Disc doping, thermal oxidation, etching and Physical vapor deposition.

Coursework and Projects

ECE 546 VLSI System-- Design 128-bit synchronous SRAM Physical Design Designed a 128-bit synchronous SRAM in standby mode using 15nm Fin FET technology libraries at 0.8 V supply voltage using Cadence Virtuoso. Optimized the design for the minimum product of energy, delay, and area.

ECE 733 Digital Electronics-- Transceiver and Equalizer Design:

Design of a 1-bit wide 45nm Digital Transceiver capable of operating at 5.7 GHz achieving a BER of better than 10 12 over a 100cm lossy transmission line. It has a post-cursor fixed weight equalization circuit having 2 taps to equalize the channel.

ECE 733 Digital Electronics-- Low Power AMD Pulse Triggered Flip Flop: Design and Optimization of a Pulse Triggered Flip Flop for low power using various sizing and Multi threshold transistor techniques achieving a power of 7.9 μW within specified timing constraints i.e. Td q <100 ns and t_Aperture < 75 ns.

ECE 739 IC’s & Fabrication Fabrication and Characterization of Ring MOSFETs, PN Junction diodes: Used Various Industry Standard fabrication techniques to simulate the characterization of MOSFETs and PN Junction Diodes and testify their respective functionality.

ECE 520 ASIC Design--ASIC Hardware Accelerator Inversion of Tri-Diagonal matrix:

Designed a Pipelined Hardware Accelerator to compute the inversion of a 10x10 tridiagonal matrix in Verilog RTL. Used Design Ware Library to integrate components and Synopsys Design Vision to perform synthesis; Optimized for Area Delay product.

ECE 745 ASIC Verification-- Verification of LC3 Microprocessor (System Verilog):

Developed hierarchical test bench for functional verification of LC3 microcontroller. Implemented Monitor, Driver and Scoreboard modules on multiple DUT Interfaces with Transaction-level modeling. Generated Constrained Random test cases to drive stimulus and created coverage model to comply with verification plan by writing Cover groups and Coverage bins.

ECE 561 Embedded System-- This side Up-Energy Optimization (FRDM-KL25Z Board):

Prototyped an orientation monitoring device on KL25Z microcontroller board. The angular tilt of the device is monitored by flashing multiple LED’s – Red, Yellow, and Green for different angles. Optimized the code to maximize the energy used by the device – function 12 minutes for a 30-second capacitor charge.

ECE 521 Computer Design Technology-- Cache Simulator (C language): Modelled an L1 + L2 level cache configurable simulator with LRU, Pseudo-LRU and FIFO replacement policies. The simulator models Inclusive, Non- inclusive and Exclusive inclusion policies. The functionality is verified by comparing processor set instructions on the simulator.

Real-Time Automated Agricultural System (Undergraduate Capstone): Used ARM 7 architecture based microcontroller to monitor moisture, temperature and humidity of the soil along with water level in storage. Developed a GSM integrated system to provide real-time information to the user via SMS and modernize irrigation practices of a farm.

Line Follower Robot (Undergraduate):

Designed an Arduino based line follower robot. The bot detects the black line on the ground based on a feedback mechanism which ensures the course and maneuvering of the robot.

Achievements

• Secured first runner-up position for line follower competition in AHVAAN Tech Fest 2013, an event organized by Gujarat Technological University.

• Best Art Entry Award by Camlin India for creativity and artistic excellence.



Contact this candidate