DANIEL S. MCNAMARA
Winston-Salem, N.C. 27101 firstname.lastname@example.org Cell: 336-***-****
A proactive, forward thinking Sr. Analog IC Layout Engineer with 24 years analog/mixed signal layout and 10 years engineering tech experience, working on custom analog/mixed-signal IC layout designs using VirtuosoXL(version IC6.1.6&6.1.5, and briefly 6.1.7), Composer schematics; and Calibre, Assura, Hercules for verification, with Star-RC for parasitic extractions. Also used Virtuoso Custom Router (VCR), and Astro Digital Place&Route tools. Processes used include: TSMC 28nm/40nm, GF 28nm, SMIC 40nm, IBM 180nm SOI and 180nm BICMOS, TowerJazz 180nm SOI, TSMC 0.6, 0.35 and 180nm CMOS/BiCMOS. A solid background in basic electronics(ASEET) and semiconductor process technologies strengthen my position.
Advanced layout techniques on critical analog blocks, such as high speed/high res ADC’s, VCO’s, LNA’s, etc, were utilized including: use of common-centroid, interdigitation and dummies for optimum matching of differential circuitry, isolation of sensitive devices using guard-rings/substrate rings, extra substrate contacts for 'latch-up' protection, matching and/or minimizing wire lengths and widths for RC control, shielding wires as needed and other practices for reducing unwanted parasitics.
SEQUANS COMMUNICATIONS - Burnsville, MN (July 2017 - Sept 2017)
Contract Sr. IC Layout Designer with Triple Crown Consulting - Austin, TX
Did layout of various blocks for the Trans/Receive(tx/rx) section of a “Narrow Band-Iot" chip, including: complex Ibias, IF amps, Temp Sensor Bias and Opamp blocks, LNA Output Buffer.
Process used: TSMC 40nm. Tools used: VirtuosoXL (v 6.1.6) and Cadence PVS for verification.
ANALOG DEVICES - Wilmington, MA (Six month contract, only lasted for month of May 2017)
Contract Sr. IC Layout Designer with Imperial Staffing - Austin, TX
Laid out complex differential amplifier with bias, feedback caps and reference sub-blocks.
Process used: TSMC 40nm. Tools used: VirtuosoXL (v 6.1.6) and Calibre for verification.
ON SEMICONDUCTOR - Corvallis, OR (Sept 2016 - Nov 2016)
Contract Sr. IC Layout Designer with Black Diamond Networks - Andover, MA.
Worked on digital row/column logic blocks associated with automobile windshield image sensors. Utilized VirtuosoXL for layout and Calibre verification. (Note: Contract cut short because of a medical procedure.)
INTEGRATED DEVICE TECHNOLOGIES (IDT) - Duluth, GA (Dec 2015 – July 2016)
Contract Sr. IC Layout Designer with IDT’s internal staffing – San Jose, CA.
Worked on the standard logic sections of “phase blenders”, “delay circuits”, band-gap opamp, and other sub-blocks associated with the “Data Buffer” of a “Load Reduced DIMM”. Process used: GF 40nm.
PERASO TECHNOLOGIES - Toronto, Canada (June 2015 – Aug 2015)
Contract Sr. IC Layout Designer with Triple Crown Consulting – Austin, TX.
Put together complex ‘ibias’ blocks for the RX and TX sections of a mm-wave product.
Process used: Global Foundries 130nm. Tools used: VirtuosoXL (v 6.1.6) and Calibre for verification.
QUALCOMM - San Diego, CA (Sept 2014 – Nov 2014)
Contract Sr. IC Layout Designer with Collabera – Morristown, NJ.
Made optimized modifications of standard logic circuitry in the flattened data format.
Processes used: TSMC 28nm and Global Foundries 28nm. Tools used: Virtuoso(v 6.1.5) and Calibre.
HUAWEI TECHNOLOGIES – High Point, NC (Nov 2013 – Mar 2014)
Contract Sr. IC Layout Engineer with Adroit Resources – Fremont, CA.
Worked on the “TX” and “PLL” sections of an LTE(Long Term Evolution) transceiver chip for cell phones.
Sub-blocks completed included a “Phase Detector” for the PLL, “main bias” for transmit section and an “ibias” cell for TX filter. Assure accurate matching of bias blocks, minimize wire resistivity/capacitance.
Technology used was SMIC 40nm process. Tools used: VirtuosoXL, Calibre and Assura.
RF MICRO DEVICES - Greensboro, NC (April 2012 – Oct 2013)
Contract Sr. IC Layout Engineer with TRC Staffing – Winston-Salem, NC.
Worked in the SSCPL group (Switch and Signal Conditioning Product Line), performing analog IC layout on chips for broadband switches in cell phones.
Worked with IBM’s 180nm CSOI7RF “Silicon-on-Insulator”, and Tower-Jazz 180nm cs18m1 SOI processes for RF (Radio Frequency) applications.
Tools used: VirtuosoXL (v 6.1.1), Composer for schematics, Calibre & Assura for verification.
Authored an in-house training paper titled “Introduction to VirtuosoXL” to allow circuit and layout designers to get a basic introduction on the use and benefits of using VXL in all layout tasks.
CADENCE DESIGN SYSTEMS - Cary, NC (April 2011 – Sept 2011)
Contract Sr. IC Layout Engineer with Additional Contract Services -- Billerica, MA.
Worked on blocks associated with the core of a Synthesizer chip for specialized Receiver/Transceiver application.
Technology: IBM 180nm BiCMOS process. Tools: VirtuosoXL, Assura verification, Composer schematics.
Used common-centroid and/or interdigitation techniques for differential input pairs and current mirrors. “Copy and mirror” strategies, along with dummy devices, were utilized for precise differential matching.
ANALOG DEVICES - Greensboro, NC (August 1999 – January 2009)
Sr. IC Layout Designer
Designed layouts of custom analog/mixed-signal IC's using TSMC 0.6, 0.35 and 180nm CMOS and BiCMOS, also 65nm for a short time. Tools utilized included: VirtuosoXL, Hercules and Dracula for verification with StarRC for parasitic extraction; also VCR, Composer and Astro digital P&R.
Extensive experience in pipeline ADC cores, S/H and differential amplifiers, switched capacitor networks, references, main bias and clock blocks and other support cells for high-speed/high-resolution ADC’s.
Achieved a considerable reduction in layout time through research and discovery of an alternative, automatic procedure for adding DNW (Deep-Nwell) and Nwell polygons, previously a manual task. Developed an in-house tutorial to document this procedure for company wide viewing.
First Layout designer in my group to use and debug for our CAD group, a TSMC 180nm DNW process, saving about 50% in future layout time while helping circuit designers optimize designs.
CADENCE DESIGN SYSTEMS - Cary, NC (July 1998 – August 1999)
Sr. IC Layout Engineer
Specialized in receiver/transceiver chips for base-station applications, using TSMC 0.35um, Lucent 0.24um and HP 0.18um CMOS and BiCMOS.
High design emphasis on common-centroid/interdigitated differential inputs and bias devices.
Developed a strong knowledge of advanced layout tools such as Virtuoso DLE (now called VirtuosoXL), DIVA (verification) and IC Craftsman analog auto-router (now called VCR).
ANALOG DEVICES – Greensboro, NC/Wilmington, MA 1986 – 1998
Sr. IC Layout Designer (February 1992 – July 1998)
Duties included: IC layout of high-resolution audio codecs at the cell level, block level and top level with full verification, as well as, PC board and MCM(multi-chip module) layout. (Also, 6 yrs as Engineering Tech.)
For IC Layout, developed expertise in Virtuoso, Dracula for verification and Composer for schematics.
Processes utilized were TSMC 0.8um, 0.6um and 0.5um BiCMOS.
Received spot bonus from project manager for identifying design flaw in a new chip layout resulting in production time savings of 6-8 weeks and mask set savings of roughly $100,000.
University of Massachusetts- Lowell, Lowell, MA 1983 - 1990
Completed 72 credits and achieved an ASEET degree in the evenings while working daytime. GPA: 3.25