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Design Engineer Electrical Engineering

San Jose, California, United States
February 02, 2018

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**** ***** *** #*

San Jose, CA. *5126


Summary of Qualifications

15+ years experience as Analog CMOS and Bipolar IC Designer.

Design Supervisor, Team Leader. Mentor.

Expert in CMOS and Bipolar processes and how the processes affect device characteristics, layout, latch-up, and ESD.


Seeking Principal/Staff design engineer position.

Open to full time and contract assignments


BS Electrical Engineering Stanford University, Palo Alto, Ca.

BA Management Engineering Claremont Mens College, Claremont Ca.

Employment History and Accomplishments

Vector Integrated Inc. Feb. 2017 to June 2017

Contract Design Engineer for Start-up Company

Set up design environment and designed analog blocks for new EE devices.

Atmel Corporation July, 2010 to July, 2016

Technical Staff Engineer April, 2015 to July, 2016

Led design team on single wire interface for Single Wire EE device selling millions of units to multiple customers.

Assigned by company CEO to bring a critical project for Apple back on schedule. The project was completed on time and is currently in high volume production.

Mentored younger engineers in design and methodology.

Principle Design Engineer July, 2010 to April, 2015

Lead designer on a multi-site team designing a low noise LDO. Final product met design goals and had near best in industry noise performance.

Led design effort to redesign Serial Temperature Sensor for high volume production.

Design of Bandgaps, Power On Reset, and Dixon Charge pumps for several Serial EE’s in different processes.

Adesto Technologies July, 2009 to Oct, 2009

Contract Design Engineer

Developed and recommended design changes for the bandgap and column amplifier designs.

Nevada County Community Network Aug. 2000 to Aug. 2008

Chairman of the Board

Founded, organized, and guided startup non-profit internet service provider to help bring internet to schools, businesses, and the public in rural Nevada County.

Linear Technology Corp. July, 2003 to April, 2009

Senior Design Engineer

Optimized die area, analyzed current flow and metal migration for large Nch and Pch switches by developing a novel design and verification method.

Specified and was sole designer of a configurable 3A/1A or 2A/2A dual synchronous Buck Converter; LTC3546.

Specified and was sole designer of LTC3417, LTC3417A-1, and LTC3417A-2 1.5A/1A dual synchronous Buck Converters.


Staff Engineer

Architected and designed a compact, low power, 100K samples per second 10+ bit Cyclic A/D in a 0.34u CMOS process for on chip temperature sensor.

TDK Semiconductor, previously Silicon Systems.

Analog Group Manager for Modem and Smart Card Design

Led design projects, mentored younger engineers, wrote performance reviews.

Principle Design Engineer

Project leader for design team of three engineers redesigning 10/100 Ethernet PHY for die size and cost reduction.

Senior Design Engineer

Specified and designed V.90 modem Analog Front End for domestic and international.

Advanced Micro Devices

Analog Design Supervisor

Managed a team of six engineers pushing state of the art CMOS

Senior Design Engineer

Design and redesign of 8bit and 12bit high speed Digital to Analog and SAR Analog to Digital converters.


“Stress Relief for Plastic Encapsulated Devices” Patent Number 8,847,291

“Voltage Reference with Low Sensitivity to Package Shift” Patent Number 9,013,231

“Temperature compensation for trans-hybrid loss in a miniaturized data access arrangement” Patent Number: 5,506,900

“Temperature compensated exponential gain control circuit” Patent Number: 5,030,924

“High speed static RAM sensing system” Patent Number: 5,068,830

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