Driver Power

P. Magesh Kannan

EXPERIENCE SUMMARY

*-***** ** ********** ** Analog and Mixed Signal design and verification.

Solid experience in ADC, DAC, Comparators, DC-DC Boost Converters, PWM, VCDL, VCO.

Designed complex Analog Mixed Signal blocks (ADC, DAC) for the high-speed VLSI circuits.

Familiarity with industry-standard circuit design and verification tools, flows and methodologies.

Hands-on experience in 22nm, 32nm, 45nm, 65nm, 90nm, 0.18μm process nodes.

Performed transistor level Circuit simulation of various Analog, Digital, Mixed Signal and RF circuits

Hands-on experience in LDO, Clock Recovery Circuits, PLL, LVDS, SerDes Blocks

Familiarity with low power techniques: DVFS, MTCMOS

Experience in Cadence Virtuoso ADE: 12 Years (Cadence Certification) SKILLS: (EDA TOOLS, LANGUAGES)

Schematic Tools: Cadence Composer-Schematic, Analog Design Environment, AMS

Simulators: Cadence Spectre, Spectre-RF, Ultrasim, etc.

Layout: Cadence Virtuoso Layout Editor, Assura

Hardware Description Languages: VHDL, Verilog

PROJECTS

16-BIT PIPELINED ADC CORE

Technology: 65nm

Description: Single channel 16-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at a sample rate of 125 Msps Specifications: Single 3 V supply, Input bandwidth, 600 MHz, Sample rate, 125 Msps, SNR, 73 dB, INL 4 LSB, DNL 0.95 LSB (typical), Power dissipation, 570 mW Responsibility: Design and implement the ADC core. DESIGN OF A 4-BIT FLASH ADC FOR UWB APPLICATIONS

Technology: 45nm

Description: The proposed ADC architecture employs the proven capacitive interpolation, which greatly reduce the power consumption, by eliminating the need of a power hungry resistive ladder.

Specifications: Supply Voltage=1.8 V, Input signal frequency=330 MHz, sampling rate of 1.2 Gsps, SNDR=25.3 dB, SFDR=29.3 dB, Power Consumption=130 mW Responsibility: Design and implementation of the ADC core. 8-BIT 150-MSPS TIME-INTERLEAVED ADC

Technology: 65nm

Specifications: Supply=3.3 V, Sampling Speed=200MHz, power dissipation of 212 mW, SNDR = 48.67, ENOB = 7.79, DNL= 0.6LSB, INL= 1LSB, Total area=1.8mm 1.8mm. Responsibility: Design and implementation of the ADC core. THERMOMETER-TO-BINARY DECODERS FOR HIGH-PERFORMANCE FLASH ADCS Technology: 45nm

Specifications: Supply Voltage=1.8V, Sampling Frequency=1.2 GHz, ENOB=5.8, Area= 0.41 mm x 0.41 mm, Power Dissipation=190 mw.

Responsibility: Design and implementation of the ADC core. 8-BIT SUCCESSIVE APPROXIMATION ADC WITH VARIABLE SAMPLING RATE Technology: 45nm

Specifications: Supply voltage=1.8V, Sampling Frequency=125 Msps, Resolution=6 Bits, INL=0.3 LSB, DNL=0.3 LSB, Power dissipation=3.8 mW.

Responsibility: Design and implementation of the ADC core. 16-BIT TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER USING RESISTOR-ARRAY SHARING

Technology: 65nm

Specifications: Supply Voltage=1.2V, Sampling Frequency=2.5 Gsps, SNDR=18.6 dB, INL=0.52 LSB, DNL=0.52 LSB, Power Consumption=22 mW, Area=0.27mm2. Responsibility: Design and implementation of the ADC core. 16-BIT SINGLE-CORE DIGITAL-TO-ANALOG CONVERTER FOR COGNITIVE ULTRA-WIDEBANDS Technology: 65nm

Specifications: Supply Voltage=1.2V, INL=0.16 LSB, DNL=0.152 LSB, Power Consumption=30 mW. Responsibility: Design and implementation of the ADC core. SINGLE INDUCTOR EIGHT CHANNEL LED DRIVER FOR DISPLAY BACKLIGHTING APPLICATIONS Description: To minimize the dynamic power consumption of the DC-DC Boost Converter based LED driver for display backlight applications by reducing the unwanted switching activities Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180nm, Switching Frequency: 93.75 kHz, Counter Clock Frequency: 1.5 MHz, Supply Voltage: 12 V, Temperature: 27 C, Inductor

(L): 1 mH, Capacitor (C): 10 μF, Input Voltage=12V, Output Voltage=24V, Max. LED current per Channel=300 mA,No. of Channels=8, Peak Efficiency=96.26%, Max. Current Balancing Error=1.33%, Min. Current Balancing Error=0.019%, Average Current Balancing Error=0.451%, Total Power Consumption=8.746 W.

LINEAR DIMMABLE LED DRIVER FOR LOW POWER AUTOMOTIVE LED LIGHTING Description: To design an LED driver which consumes minimum area and to achieve high linearity to minimize the flickering effect

Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180 nm, Current per Branch=25 mA, No. of Branches: 4, Total Current=100 mA, Supply Voltage=4 V, Temperature=27 C, Dimming Control Voltage=0 - 4 V.

TEMPERATURE AWARE LINEAR DIMMABLE LED DRIVER

Description: To design and implement temperature aware LED driver to improve the linearity and to operate the LED driver for wide range of temperatures Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180 nm, Supply Voltage=5V, No. of Branches: 10, Current per Branch=10 mA, Total Current=100 mA, Simulation Temperature=27 C, Temperature Analysis= 50 C-160 C. LEAKAGE AWARE LED DRIVER

Description: To minimize the leakage power of the LED driver during energy saving mode Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180 nm, No. of Branches=4, Current per Branch=25 mA, Total Current=100 mA, Supply Voltage=4 V, Dimming Control Voltage=0-4 V, Temperature=27 C, Leakage Power=68.41 fW, Static Power=507.39 mW. High-Speed LED Driver for Visible Light Communications Description: To improve the switching speed of the LEDs by remaining charge carrier sweep-out mechanism for Visible Light Communication.

Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180 nm, DC-DC Boost Converter Switching Frequency=2.5 MHz, Supply Voltage-1 (Vdd1)=12 V, Supply Voltage-2 (Vdd2)=1 V, Temperature=27 C, Load Resistors: R1=51 Ω, R2=1.5 KΩ, Delay: Dual supply without Carrier Sweep out=20.36ps, Delay: Dual supply with Carrier Sweep out=4.84ps, Power: Dual supply with Carrier Sweep out=33.466 mW, Power: Dual supply with Carrier Sweep out=10.451 mW.

Temperature Aware Linear LED Driver with Minimal Leakage and Inrush Current Description: To design and implement an DC-DC Boost Converter based LED driver with minimum inrush current during the start-up.

Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180 nm, Supply Voltage (Vdd)=(2.7V- 5.5V) V, Control Voltage (Vctrl)=(0-5) V, Simulation Temperature =27 C, Max. Current=200 mA, Temperature Analysis= - 40 C to 85 C, Dynamic Power=1041.3 mW, Leakage Power=52.244 μW.

Multi-Partition Switching Based Low Power On-Chip LED Driver with Minimal Inrush Current Description: To design implement a novel multi-partition based interleaved switching technique minimize the inrush current in DC-DC Boost Converter. Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180 nm, Switching Frequency=100 kHz, Supply Voltage=12 V, Operating Temperature: -25 C to +125 C, Inductor (L)=1 mH, Capacitor (C)=10 μF, Inrush Current=2.405 A, LED Current=502.2 mA, leakage current=27.55 μA, Power=8.862 mW.

Voltage Controlled Delay Line Based Pulse Width Modulation Scheme for Low Power LED Driver Description: To design and simulate a Voltage Controlled Delay Line (VCDL) based PWM signal generation for DC-DC Boost Converter.

Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180 nm, Switching Frequency=100 kHz, Supply Voltage=12 V Input Voltage=12 V, Max. Load Current=300 mA, Temperature=27 C, PWM Range=1% – 99%, Leakage Current=43.98 μA, Power=4.08 W. MTCMOS Based Soft-Start Circuit for On-Chip LED Driver with Minimal Inrush Current Description: To design and simulate a novel MTCMOS based soft-start circuit for On-Chip LED driver to minimize the inrush current during start-up

Specifications: Simulation Tool: Cadence Virtuoso ADE, Technology: 180 nm Switching Frequency=100 kHz, Supply Voltage=5 V, Maximum Load Current=500 mA, Temperature=27 C, Inductor

(L)=1 mH, Capacitor (C)=10 μF, Max. Inrush Current=359.11 mA, Leakage Current=0.03173 μA, Power=1.592 mW.

EDUCATION

Ph.D in Pondicherry Engineering College, Pondicherry (2017) P.G. Dip. In Intellectual Property Rights, Annamalai University (2011) M.Tech. VLSI Design: May 2005, CGPA: 8.65/10.0 TIFAC-CORE, SASTRA University, Tanjore, Tamilnadu, India. B.E. Electronics & Communication Engg. : July 1997, Percentage: 75.5%, Government College of Engineering, Salem, University of Madras, Tamilnadu, India.

PATENTS

1. Voltage Controlled Delay Line (VCDL) based Pulse Width Modulation (PWM) Scheme for Low Power LED Driver. (Application No: 201*********, Date: 20-10-2016) 2. Area Efficient On-Chip Active Inductor based Low Power LED Driver.

(Application No: 201*********, Date: 20-10-2016)

3. Temperature Aware EMI Free Adaptive PWM Pulse Generation for DC-DC Converters. (Application No: 201*********, Date: 20-10-2016)

4. Ultra-Low Leakage DC-DC Boost Converter based LED Driver for Smart Phone Display Backlight Applications.

(Application No: 201*********, Date: 20-10-2016)

5. A Novel Decoder Based Single Inductor Eight Channel LED Driver for Low Power Display Backlight Applications. (Application No: 201*********, Date: 20-10-2016) PROFESSIONAL EXPERIENCE

Total Experience: 20 Years

Tech Lead: Analogix Technologies, Pondicherry: June 2013 to November 2017 Design Engineer: GDA Technologies, Chennai, June 2007-April 2009. Asst. Prof (Senior Grade): ECE, SRM University, Kattankulathoor, July 2012 – May 2013 Asst. Prof (Senior): VLSI Division, VIT University, Vellore, June 2009 – June 2012 Lecturer: VLSI Division, TIFAC-CORE, SASTRA University, Tanjore, June 2005-May 2007. Lecturer - Rajiv Gandhi College of Engineering & Technology, Pondicherry, Jan 2002 to August 2003. Lecturer: Mailam Engineering College, Mailam, July 2001 to December 2001. Customer Support Engineer: Peripherals Care, Pondicherry, October 1997 to May 2001. PERSONAL DETAILS

Date of birth: 10-07-1976.

Sex: Male.

Nationality: Indian.

Languages: English, Hindi, Tamil

Contact: 960*******

Email: *************@*****.***

Contact this candidate