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Manager of Design Verfication of data for Quality Rls for Fabrication.

Cedar Rapids, Iowa, United States
December 30, 2017

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Edward H Schultz

**** ********** **, ****** **** 52302

Home 319-***-****

Cell 714-***-****

I'm seeking to be part of a team, in a successful company so I can use my knowledge and background, to make the company more successful.

I have worked as a Engineer Manager for over 20 years, in both Quality and data verification releasing data to several Fabrication company's for wafer starts.

I have the ability to work by myself, or work with a group as a Team player, to get any job completed in the time needed for a project to be successful. I'm extremely dedicated and a dependable hardworking individual, with attention to detail. I take pride in my work to always ensure the outcome is correct.

If needed I will step up and cover for others when they are out or if there is a heavy workload . I take pride and ownership in all projects and or tasks. I am a certified Quality Auditor and have participated in many Company ISO Audits.

I have managed the work of 12+ Design engineers and 15 Program managers, making sure that the final data that was produced after verification was 100% correct so I could then release the data for Fabrication to produce the next generation of Wafer starts of parts for the necessary customers.


SKYWORKS SEMICONDUCTOR, Cedar Rapids Iowa (June)2014-2016


Current Profession Design/Fabrication

Manager -Senior Quality Design, of Design and Product Quality

Inspected and verified data input from Design Engineers, making sure it passed specifications. Provided foundry locations and entered purchase order numbers and total mask costs into release documents. Interacted across most functional areas to ensure projects were completed correctly and timely so data sent for fabrication to masks encountered no issues.

Basic Job Description

Act as main contact for all tasks related to Si CMOS and SOI releases to WFE. ( Wafer Fab Silicon).

My roles and job duties were as follows, understood and performed as detailed.

A ) Si release Coordinator.

B ) Maintain Calendar & Tape Out Log in Sky Foundry.

C ) Review Releases to determine that the appropriate mask & wafer PO (purchase orders) already exist or have been created.

D ) Request and obtain release permissions from Design Managers.

E ) Understand and clearly document in Tape out description in Sky Foundry Lot breakdown.

F ) Generate/update basic Version assignments spreadsheet for each wafer release .

G) Maintain Tape out directories.

H ) Generate simple reticles.

I ) Preliminary complex reticle/25R feasibility using Version Assignments spreadsheet.

J ) Approve reticle map from Foundry as needed.

K ) Perform Sky Foundry submittal for Fabrication.

L) Archive the Final data used.


*** Worked at Rockwell Collins in Newport Beach California ***

(before their move to the Midwest)


TOWER JAZZ SEMICONDUCTOR New Port Beach, Ca 1994 -2013

(Includes Aerospace Quality Technologies)

Current Profession Design/Fabrication

Manager-Technical Design Engineer with extensive experience in JC Semiconductor environment, accepting customer input, and reviewing, running, verifying and releasing data used in product creation. Interact with 17Program Managers, and finance to ensure timely release of products. Pro-active, with excellent communication skills and a focus on increased efficiency with decreased expenses. Known for finalizing data with high quality results. Areas of expertise include:

A) Release of all CMOS / SOI data to Fabs • Set up Version Assignments.

B) Daily Project Tracking of project PO's • Verify data extents in Version Assignments.

C) Final Review & release of Data from Layout • Generate Reticle plans for projects.

D) Maintained Tape Out log of all data sent • Review & OK Packaging reticle plans.

E) ** Project Management I Archiving ** Main contact for CMOS / SOI releases.

F) ** In – House EMS Lead Auditor for Company ** ISO 9000, External Audits.


Provided daily follow-up for all customer and internal wafer sets in Fab areas, to make sure there was no stoppage in parts being developed.

Worked with 15 plus Program managers to assist on correcting any wafer I mask cost issues.

Sent out and requested okay on release permissions from Lead design managers on all projects after attending final design reviews, before releasing data for masks and wafers.

Recognized as "go to" person to solve any work flow issues or problems.


A) In a phase of 17 years, I had a 98% error less success rate

of all data sent out to Wafer Fabrication for customer parts.

B) I'm a certified Quality Auditor and that has participated in many

Company audits.


BA, Criminal Justice, Golden West College, Huntington Beach California 92648 - 1999-2001

AA Microchip Layout Design, Orange Coast College, Costa Mesa California 92646 - 2005

Technical Degree 50 hours - "IT" School,@ Integrated Digital Technologies. Corp. Irvine California. - 2005


Fab Process and Development of Wafers

SiGi Design, Electrical Development Professional background.

Attended Management Workshops

Certification and Completion of P.O.S.T (996 hours), Top 5 in the class at

Orange County Sheriff's Training Facility Reserve Police Officer

(Worked for LOOMIS Armored Jumper & Driver (money collection) before becoming Police Officer)


Cad Manager / SAP input

Worked 2 years in a Fab to understand processes procedures on wafer sets. Identifying Yield Mask Parameter issues

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