Student

Spoorthi Shankar Kotrannavar

***, * ***** ******, *** 110 +1-602-***-****

Tempe, AZ 85281 ********@***.***

OBJECTIVE

Seeking fulltime positions in the field of Wireless Communications and Digital Design implementation where my initiative and desire to learn will contribute towards the productivity of the company. Keywords: LTE, CDMA, OFDM, MIMO, DSP, TCP/IP, Communication Systems, Communication Networks, DSP Algorithms, ASIC, RTL Design, Digital Design, FPGA, Hardware Acceleration EDUCATION

Arizona State University, Tempe, AZ Expected: Dec 2017 MSE in Electrical Engineering 3.64/4

Visvesvaraya Technological University, India May 2012 B.E in Electronics and Communication Engineering 84.82/100 PROFESSIONAL EXPERIENCE

Qualcomm Technologies May2017 to Aug 2017

Interim Engineering Intern

Worked on Fixed point FFT modelling for 5G NR technology in Modem Hardware Team.

Gather FFT requirements for LTE and 5G NR 3GPP initial releases.

Evaluate various radix combinations into which the FFT can be decomposed.

Compute the complexity/tradeoffs associated with each decomposition.

List and evaluate FFT decomposition using the Cooley-Tukey decomposition into multiple stages using radix 2,3,4,5 butterfly implementations. Evaluate potential performance gains using larger radix sizes.

Code fixed point models for the core butterfly structure. (Re-use and edit existing code)

Measure the performance difference between fixed point FFT with an ideal floating point Matlab implementations

Generation of computing primitives for 5G Cyclic Prefix & Windowing Transmit block Coding of adder, multiplier & inversion primitives in C++ Skills: C++, Matlab/Octave

IBM India Pvt Ltd Sept 2012 to Dec 2015

Associate System Engineer (Telecommunications sector) Worked for IBM's telecommunication sector as an Application Developer. Involved in Application Design, Tools development and existing service & application maintenance for AT&T, Telstra and A1 Telekom. Skills: C/C++, Linux, Shell scripting, SQL

TECHNICAL SKILLS

Programming and Scripting Languages: C/C++, VHDL, Verilog, Shell, Python, Perl, SQL Operating Systems: Windows, LINUX

Software Packages/Application Tools: MATLAB,SIMULINK, Cadence-Virtuoso Schematic Editor and Layout Suite, HSPICE, StarRC, Hercules DRC, LVS, SQL Developer, NexysTM4 DDR Artix-7 FPGA Board, Xilinx Vivado Design Suite System Edition, Mentor Graphics ModelSim, Synopsys Synphony Model Compiler, Design Compiler, Synplify Pro, VCS

RELEVANT COURSES: Random Signal Theory, Digital Communications, Information Theory and Coding, Wireless Communications, Detection & Estimation Theory, Digital Systems & Circuits, Hardware acceleration & FPGA Computing, VLSI Design, Communication Networks, Time Frequency Signal Processing. PROJECTS

Channel Estimation for OFDM Dec 2016

Simulated the OFDM system with Channel Estimation for BPSK for different time domain coefficients and compared the performance using MATLAB

Simulate CDMA for an uplink channel Dec 2016

Measured the performance of a CDMA system based on the increasing number of users, channel length and a particular constant metric known as the power profiling using MATLAB Equalization for ISI Channels Nov 2016

Implemented a linear MMSE Equalizer for propagation of data through good and bad channels and compared the performance of the equalizer for different equalizer lengths using Matlab Viterbi Equalizer was also implemented for the same set of data and channels and the performances of MMSE and Viterbi equalizers were compared

Diversity Techniques over Fading Channels Sept 2016 Compared the performance of different diversity techniques like MRC, SC and GSC using MATLAB for different K-PSK constellation and diversity order for independent and correlated channels. Hardware acceleration of Bank vault security system using FPGA April 2017 Implemented the lock and key system for bank vault security using block cipher, Double Chaining algorithm on FPGA Virtix 7. Various optimization techniques were used to achieve the maximum throughput and frequency with minimum resources.

Convolution and Max Pooling Engine Design April 2017 Designed a convolution and max-pooling module, where the module input is a 4x4 pixel image, a 3x3 convolution kernel, and a shift value and the module output is the max-pooling output value. The objective of the design was to minimize area and power, while maximizing throughput Implemented the RTL design in ModelSim using Verilog and verified the functionality with a Verilog testbench. Synthesized the code and performed functional verification using APR. Design of 16word x 16bit register file with one read and one write port in 7nm PDK March 2017 Designed the 4:16 Decoder from schematics to layout including all the standard cells and integrated the I/O circuit, register files and the decoders.

Verified connectivity and functionality through DRC and LVS checks and performed parasitic extraction and timing analysis. Optimized the design to obtain a low Energy-Delay -Area product Design of Modulo 8-bit Full Adder Nov 2016

Designed an eight bit full adder using 32 nm PDK technology constrained to low power and low Energy Delay Product using mirror adder implementation for the design of 1-bit full adder and TSPC register for the implementation of Dflipflop. Followed the ripple carry adder implementation for the integration of all 1-bit full adders and D-flipflops to design the 8-bit full adder.

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