Electrical Engineering Design

Michael (Qian) Liu

****-***@*******.*** 949-***-****

EXPERIENCE

Inphi Corporation Los Angeles,CA

Validation Engineer 2016~Present

• Post-silicon validation/characterization of high-speed circuits/systems

• Chip bring-up/debug, wafer/bench testing, RF/analog metrics evaluation, data analysis and reporting

• Test system design and test plan development, test board design/debug, test automation in Python

• Coordinate with design/system/AE/PE/FW to perform design debug, customer support, etc Broadcom Corporation Irvine, CA

RF DVT Intern 2015~2016

• WiFi/Bluetooth chip bring-up, verification/optimization of RF/analog and system level performance

• Measure and optimize parameters like phase noise, noise figure, IQ imbalance. EVM, BER, sensitivity, etc

• Test automation development in Perl, Python and LabVIEW to reduce test time significantly SKILLS

• Test Equipment: Network Analyzer (up to 110GHz), Spectrum Analyzer, DCA Oscilloscope, etc

• Simulation Tools: ADS, Cadence, Ansys HFSS, OrCAD

• Test Automation Platform: Python, Perl, C, Matlab, LabVIEW EDUCATION

University of California, Irvine Irvine, CA

M.S. in Electronics and Electrical Engineering 2014~2016 Major GPA: 3.8/4.0

University of Glasgow Glasgow, UK

B.S. in Electronics and Electrical Engineering 2012~2014 Tianjin University Tianjin, China

B.S. in Electronics and Electrical Engineering 2010~2014 Irvine, CA

PROJECTS

Design of a PLL-based Frequency Synthesizer 2015

• Designed a quadrature VCO with large tuning range by using varactor

• Implemented a frequency divider by incorporating ILFD, CML and CMOS topologies

• Employed PFD, charge pump, and loop filter to form the entire PLL

• Achieved locking condition and a low phase noise at 1MHz offset Two-Stage Fully-Differential Op-Amp Design 2014

• Designed a two-stage fully-differential folded-cascode op-amp in CMOS process

• Employed common-mode feedback and frequency compensation to increase the op-amp stability

• Achieved high DC gain, high bandwidth, large phase margin and large output swing Crossbar Switch Design in Digital System 2013

Designed a crossbar switch system to route arbitrary length 8-bit word data packets

Constructed a state machine for the control module of the crossbar switch

Created clear, synthesizable VHDL code to build the system and tested it using CAD

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