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Project Engineering

Location:
Mumbai, MH, India
Posted:
September 19, 2017

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Resume:

CAREER OBJECTIVE:

Seeking an opportunity in prestigious company where my skills and capabilities can be put to efficient use and provides new challenges for personal as well as professional growth while contributing in the productivity of the company. PERSONAL INFORMATION:

Name: Neha Sharma

Date of Birth: 21-12-1993

Contact Details: ***********@*****.***

Language proficiency: English, Hindi

WORK EXPERIENCE:

Organization: Samsung Heavy Industry India

Duration: July 2015 to Feb 2017, 1.5 year

Designation: Instrumentation Engineer

Projects:

Prebid Engineering of ONGC VASAI- Prepared Instrument Index.

Prebid Engineering of Life Extension of Well-Head Platforms Project[LEWPP-3]- Prepared Bulk MTO, Instrument datasheet of Field Instruments (Pressure, Temperature, On-off Valve, Control Valves).

FLNG Familiarization [Internal Study]- Prepared Instrument index, Instrument datasheet of Field Instruments (Pressure, Temperature, On-off Valve, Control Valves), Instrument I/O list. ACADEMIC PROFILE:

EXAMINATION YEAR BOARD/UNIVERSITY %/CGPA

B.E. BRANCH: Instrumentation

And Control engineering

2015 Netaji Subhas Institute of Technology,

Dwarka,New Delhi(Delhi University)

74.5

CLASS XII 2011 CBSE 93.4

CLASS X 2009 CBSE 89.2

ACADEMIC DISTINCTIONS:

Availed IAFBA SUBROTO MEMORIAL SCHOLARSHIP in 2011-Merit Based Scholarship are provided to the children of AF Personnel (Serving, Retired & Deceased).The scholarship is provided on a yearly basis.

Availed merit scholarship for four consecutive years during my B.E(ICE),NSIT. TECHNICAL SKILLS:

Programming Language: C/C++, MATLAB SIMULINK, VHDL/Verilog.

MS Office (Word, Excel, PowerPoint).

PROJECTS AND INTERNSHIP:

Reduction of induced time delay in networked control system(June 2013- July 2013) Reduced induced time delay in plant using PID controller and Smith predictor.

Research Intern, IIT Kharagpur(June - July,2014) Design of 32 bit RISC processor using VERILOG language- and modelling of its component using VERILOG language. Along with sequential and combinational building blocks of non-pipelined processor such as adders and registers more, complex blocks i.e. ALU and Memories had been designed and simulated.

Final year Project in B.E(ICE),NSIT(Jan-May,2015) Novelty Detection using Double Weighted Methodology to handle the concept Evolution in Data Streams It is an algorithm to solve concept evolution problem occurs in data stream classification. Concept Evolution problem is addressed by detecting the novel class instances (those instances which were not classified by the existing classifiers) and then adding an classifier in ensemble to classify them into a new class called Novel Class . POSITIONS OF RESPONSIBILITY:

Senior coordinator, Documentation and publicity department in INNOVISION 2013(Technical Fest of College).

Organiser of event TURNCOAT in MOKSHA 2012(Technical Fest of College).

Worked at neighbourhood project-It is a non-profit club for welfare of underprivileged kids. Student volunteers provide tutorial guidance to kids in primary education. I was volunteer of Kriti(Annual fest of neighbourhood project).



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