Design State University

SUGANESH KUMAR

**** **** ****** #***, **********, CA 95825. Ph:806-***-****, Email:************@*****.*** OBJECTIVE:

Actively seeking full-time position in VLSI, Firmware, Verification or Computer Architecture, where I can apply my technical & programming skills and contribute effectively to your organization. EDUCATION:

MS in Electrical and Electronics Engineering, CSU Sacramento, CA GPA:3.9/4.0 BE in Electronics and Instrumentation Engineering, AIHT, India GPA:3.7/4.0 AWARDS:

1. Spot Award at Infinite Computer Solutions, Chennai, India 2. Intel Recognition Award for Power frequency coverage tool, Folsom, CA RELEVANT COURSEWORK:

Dec 2017

May 2013

Analog & Mixed Signal IC Design

Digital Integrated Circuit Design

TECHNICAL SKILLS:

Languages:

Tools:

Operating System:

EXPERIENCE:

Micro-Computer System Design I - Micro-Computer System Design II Advanced Topics in Logic Design Hierarchical digital design methodology Verilog HDL, VHDL, C,C++,VC++,Perl, Assembly Language,NI LabVIEW, Synopsys VCS, Design Compiler, Xilinx ISE, Spice, Spartan3E, Cadence Virtuoso, Code Composer Studio, Mat lab, hspice, Arduino Windows 95/98/2000/XP/Vista/7/8, UNIX, LINUX

MESI, DDM,RS232, PCI EXPRESS, PCI Protocols, coherence Protocol Pre-Silicon validation intern, Intel Corporation Feb 2017- Aug 2017

Developed the code Collab indicators to check the per reviewer status in perl

Developed the PFC (Power Frequency Coverage) to cover the power signals in perl & specman

Developed the Power diff script to check whether the signals are toggled

Developed the coverage script to check the 4-week regression status Embedded Engineer, Infinite Computer Solutions July 2013- July 2015

Developed polynomial equations for Thermocouple, RTD (Resistance Temperature Detector) & Thermistor and performed code implementation in the Data processing module.

Developed DLL for the configuration storage and retrieval, shared by data processing Module and Data Communication Module.

Developed and fixed issues with the Firmware User Interface Module.

Developed Language Localization for the User Interface Module Research Assistant, California State University

Link: http://www.csus.edu/storc/people.html

Worked on Zero Net Energy Home wherein I developed the code to complete home automation.

Code Implementation with Arduino and data collection using raspberry pi 3 with a key focus on IoT. Teaching Associate, California State University

Conducting lab sessions, instructing students how to use FPGA boards and helping them throughout the course “Introduction to Logic Design”.

ACADEMIC PROJECTS:

1. Implementation of Parameterized 128 x 32 bit FIFO in Verilog HDL (Synopsys VCS, Verilog)

• Modeled 128 x 32 bit FIFO design, memory module and state machine design using Verilog and generated automatic test vectors to verify the design.

2. Design of a cache controller for a 32-bit based system:

• Designed a 32-bit cache controller using LRU and MESI protocol. Write back protocol was used to write the data into the memory.

3. Designing verification and synthesis of pipelined vector floating point multiplier: (VCS Synopsis, Verilog)

• Designed, validated, and synthesized a pipelined floating point vector multiplier in Verilog.

• This multiplies two 32-element vectors A and B, element by element, and store the products in vector C. Elements of A and B are 32-bit single precision floating point numbers. 4. Design of an Operational Amplifier: (PSpice)

• Designed a Telescopic op-amp circuit for given specifications. Determined the dimensions of the transistors based on the Theoretical definition and finetuned the op-amp performance on P-Spice to achieve the desired performance metrics. 5. Design Simulation and Layout of the 5-bit pipelined ADC in CMOS 0.18μm : (Cadence Virtuoso)

• D flip -flops were made using transmission gates and inverters.

• Control logic for ADC was implemented and schematics were drawn for the entire design using Cadence Virtuoso.

• Layouts were designed according to schematics. The conversion was made from Analog voltage to 5-bit Digital output. 6. Design and Synthesizing a Circuit in Design Compiler Using Design Vision: (Primetime, Design Compiler)

• Designed and verified four types of paths in Verilog and synthesized the design by providing constraints. Analyzed the results of the timing and area reports.

• Generated a clock signal by using the output of div-by-9 circuit to a designed sequential-sequential path circuit.

• Synthesized the unmapped net-list to get a mapped net-list and to record required timing and area reports.

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